Comparison of Strategies for Redundancy to improve Reliability - - PowerPoint PPT Presentation

Comparison of Strategies for Redundancy to improve Reliability concerning Gate Oxide Breakdown

Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann

17.02.2009, Bremen

Institut für Angewandte Mikroelektronik und Datentechnik Universität Rostock

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Outline

Basics and Motivation

Approaches for reliability enhancements Gate oxide breakdown

Redundancy strategies

Theoretical fundamentals Results

Conclusion / Outlook

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Motivation – Known approaches

• Layout modifications
• Redundancy

Yield enhancements

• Hardening techniques
• Reusing debug resources

for redundant flipflops [Mitra]

Soft error resilience Little effort put into lifetime reliability enhancements Transient failures Permanent failures Initial failures Failures occuring at runtime

Reliability

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Motivation – Known approaches

Lifetime reliability enhancements

High level:

Dynamic system management to adapt operation conditions in response to an observed hardware usage [Srinivasan et al.]

Low level:

Random insertion of redundant transistors to improve yield [Sirisantana et al.] Improvement of this approach by a controlled insertion at those instances which are most vulnerable to gate oxide breakdown [Sill et al.]

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Basics – Gate oxide breakdown

Gate oxide breakdown – GOB:

Point of time a conducting path between gate and substrate is generated Mainly dependent on:

Gate oxide thickness Electrical field at the gate

Causes:

Sudden extrinsic overvoltage: ESD – Electro-Static Discharge Slow intrinsic destruction over time: TDDB – Time-Dependent Dielectric Breakdown

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Basics – TDDB

Physical mechanism: trap creation

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Basics – TDDB

• Initial traps

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Basics – TDDB

• Initial traps

During operation: generation of overlapping traps

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Basics – TDDB

• Initial traps

During operation: generation of overlapping traps Soft breakdown: Creation of a conducting patch

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Basics – TDDB

• Initial traps

During operation: generation of overlapping traps Soft breakdown: Creation of a conducting patch Increasing current flow Heat dissipation Thermal damage

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Basics – TDDB

• Initial traps

During operation: generation of overlapping traps Soft breakdown: Creation of a conducting patch Increasing current flow Heat dissipation Thermal damage

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Basics – TDDB

• Initial traps

Finally: Hard breakdown

• R 0

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Basics – TDDB

Finally: Hard breakdown Model by Segura et al.

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Basics – Scaling issues

Scaling increases the gate oxide breakdown problems:

Increasing number of transistors within a die

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Basics – Scaling issues

Scaling increases the gate oxide breakdown problems:

Increasing number of transistors within a die Decreasing gate oxide thickness Increase of the electrical field due to non-ideal supply voltage scaling

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Theoretical fundamentals

[ ]

( ) ( )

n n t S

R t R t e λ

−

  = =  

Failure rate λSYS represents the rate at which an individual system suffers from individual faults Reliability Rsys(t) is the probability of the system to perform as desired at time t Series system with n equal components (component failure rate λ) fails if any component fails Parallel system works until all of its components fail

[ ]

( ) 1 1 ( ) 1 1

n n t P

R t R t e λ

−

  = − − = − −   ( )

SYSt

SYS

R t e λ

−

=

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Mean Time To Failure (MTTFSYS) of a system is the average time a system operates until it fails

Theoretical fundamentals

( )

SYS SYS

MTTF R t dt

∞

= ∫

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Redundancy strategies

n = no. of transistors; g = no. of gates; m = Ø no. of transistors per gate

Basic multiplier Block duplication Gate duplication Transistor duplication

( )

n t BASIC

R t e

λ −

=

2

( ) 1 1

n t BD

R t e

λ −

  = − −  

( )

2

( ) 1 1

g m t GD

R t e

λ −

  = − −    

( )

2

( ) 1 1

n t TD

R t e λ

−

  = − −    

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Simulation setup

Wallace multiplier Transistor level simulations with HSpice Industrial 65 nm gate library First order model of Segura et al.

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Results – No defects

50 100 150 200 Area Delay Overall power Static power Design Parameters Ratio to basic multiplier [%] Block duplication Gate duplication Transistor duplication

21 20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%]

Results – Reliability with defects

20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%]

0.537 No 13.552 4.237 0.446

MTTFGOB

+ 2524 % + 789 %

• 17 %

+ / -

Trans. Gate Block

Dupl.

Simulation results and theoretical curves

20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%] 20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%] 20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%] 20 40 60 80 100 5 10 15 20 25 30 35 40 Time units t R(t) [%]

0.00 20.00 40.00 60.00 80.00 100.00 0 20 40 60

No duplication Block duplication Gate duplication Transistor duplication

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0.0 0.5 1.0 1.5 2.0 2.5 5 10 15 20 Number of defects P [mW] Gate duplication, overall power Transistor duplication, overall power

Results – Graceful degradation

Increase of the delay with rising defects

0.6 0.7 0.8 0.9 10 20 30 Number of defects td [ns] 0.6 0.7 0.8 0.9 1 2 3 Number of defects td [ns] Gate duplication Transistor duplication Trend (gate duplication) Trend (transistor duplication)

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Increase of the overall power with rising defects

0.0 0.5 1.0 1.5 2.0 2.5 5 10 15 20 Number of defects P [mW] Gate duplication, overall power Transistor duplication, overall power Gate duplication, static power Transistor duplication, static power

due to increased static power consumption

Results – Graceful degradation

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Conclusion

Need of design improvements for lifetime reliability Lowest abstraction level (transistor level) promises the most improvements concerning gate oxide breakdown Simpler integration of (as well good) gate level duplication into existing design flows and CAD tools Graceful degradation behavior in the presence of defects

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Outlook

Usage of more elaborate and complex breakdown models Additional implementation of devices with different gate

• xide thickness

Partial duplication of most vulnerable gates or transistors Investigation of the impact of soft breakdowns