SLIDE 1
MTLE-6120: Advanced Electronic Properties of Materials Semiconductor - - PowerPoint PPT Presentation
MTLE-6120: Advanced Electronic Properties of Materials Semiconductor - - PowerPoint PPT Presentation
1 MTLE-6120: Advanced Electronic Properties of Materials Semiconductor transistors for logic and memory Contents: Aside: vacuum tubes Bipolar junction transistors (BJT) Junction field effect transistors (JFET) Metal oxide
SLIDE 2
SLIDE 3
Vacuum tube triodes
◮ Control plate / grid between cathode and anode ◮ Negative bias repels electrons; reduces current ◮ Small changes in voltage ⇒ large changes in current ◮ Acts as a switch or amplifier
Images: Wiki: Vacuum tubes
3
SLIDE 4
Vacuum tube computers
◮ Each triode in own separate tube ◮ ENIAC computer in 1946: 17468 such tubes ◮ Key characteristic required: three terminal device where third terminal controls current between first two ◮ In principle: computer made entirely of hydrualically or pneumatically-controlled valves!
Images: Wiki: Vacuum tubes
4
SLIDE 5
Bipolar Junction Transistor (BJT)
◮ Heavily doped emitter E (like cathode in triode) ◮ Thin lightly-doped base B (like control plate / grid) ◮ Lightly-doped collector C (like anode) ◮ Either pnp (shown above) or npn (polarities reversed) ◮ Which one does the vacuum tube triode correspond to?
5
SLIDE 6
BJT: junction potentials
◮ Two pn-junctions: E-B and C-B ◮ Normal (active) operation: forward-bias E-B and reverse-bias C-B ◮ E-B junction: depletion region mostly in base ◮ C-B junction: comparitively symmetrical ◮ Potential drop across depletion regions; negligible field in interiors ◮ Hole concentration at B-end of E-B junction: pn(0) = n2
i
Nd exp eVEB kBT
◮ Hole concentration at B-end of C-B junction: pn(WB) ≈ 0
6
SLIDE 7
BJT: current flow
◮ Diffusion current across base: IE ≈ IC = eADh
pn0 WB = eADhn2
i
NdWB exp eVEB kBT
◮ Current out of n-type base has to be electrons: two factors in α ≡ IC/IE ◮ Electron current in E-B: small due to asymmetric doping γ =
1 1+
NdWBµe NaWE µh
◮ Recombination: small for thin lightly-doped base αT = 1 − W 2
B/(2Dh)
τh
◮ Current transfer ratio α = γαT 0.99 for typical BJTs ◮ Current gain β ≡ IC/IB =
α 1−α ∼ 102 − 103
7
SLIDE 8
BJT: IV characteristics
◮ Ideal characteristic: IC = IE independent of VCB ◮ Leakage current in reverse-biased C-B junction, ICB0 ◮ At high VCB, IC = αIE + ICB0 and IB = (1 − α)IE − ICB0 ◮ But slope of IC vs VCB increases for finite IE (beyond ICB0) ◮ Early effect: C-B depletion width increases with VCB ◮ This reduces WB, making hole diffusion easier, and therefore IE ↑
8
SLIDE 9
BJT: common base amplifier
◮ Small changes in E-B potential strongly affect IC ≈ IE = IE0 exp eVEB
kBT
◮ Convert ‘amplified’ current to voltage using resistor ◮ Collector potential VCB = −VCC + RCIC ◮ Voltage gain (controlled by selecting IE and RC): ∂VCB ∂VEB = RC ∂IC ∂VEB = IERC kBT
9
SLIDE 10
BJT: common emitter amplifier
◮ Note npn-transistor: polarities reversed ◮ Current amplifier: input IB amplified by β to output IC ◮ With leakage current, IB = (1 − α)IE − ICB0 and IC = IE − IB = βIB + ICB0 1 − α
ICE0
◮ Operate at VCE > VBE, else saturation: IC limited by IE
10
SLIDE 11
Junction Field-effect Transistor (JFET)
◮ n-JFET: narrow n channel between p+ gates (reversed for p-JFET) ◮ Width of n channel determined by depletion regions ◮ Basic idea: control channel width and conduction using gates ◮ Always operate with channel potential > gate ⇒ reverse bias
11
SLIDE 12
JFET: channel IV characteristics
◮ First consider applied VDS with VGS = 0 ◮ Voltage of channel-gate junction increases from S to D ◮ Correspondingly increasing depletion width narrows channel ◮ Increase VDS, current ID increases, but channel narrows ◮ At V sat
DS, channel pinches off at D end, ID saturates
12
SLIDE 13
JFET: gate effects
◮ Apply negative gate potential: VDG increases ◮ Narrower depletion region, earlier pinch off ◮ V sat
DS = VP + VGS, where pinchoff voltage VP = V sat DS at VGS = 0
◮ Therefore, gate potential controls channel current and effective resistance ◮ Strong-enough VGS shuts off channel completely ⇒ V off
GS
◮ Empirical behaviour: IDS = IDSS
- 1 − VGS/V off
GS
2
13
SLIDE 14
JFET amplifier
◮ Amplifier: gate voltage controls channel current ◮ Convert channel current to voltage through resistor RD ◮ Vaguely similar to common-emitter amplifier ◮ Set operating ‘quiescent’ point at center of
- perating range
◮ Signal amplitudes small enough to stay in range ◮ Voltage gain ∂VDS ∂VGS = RD∂IDS ∂VGS = 2IDSSRD V off
GS
- 1 − VGS
V off
GS
- 14
SLIDE 15
Metal-oxide-semiconductor (MOS) capacitor
Metal Oxide Semiconductor Metal Oxide Semiconductor Metal Oxide Semiconductor
◮ Metal and SC separated by an insulating oxide: why don’t the bands bend? ◮ Apply potential: linear variation in oxide, typical bending in SC ◮ Vacuum level (potential) continuous, D⊥ continuous ◮ For p-SC and positive Vmetal, CB bends towards EF ◮ For Vmetal > Vth (threshold), CB closer than VB to EF ◮ Inversion region: n > p in p-type semiconductor ◮ Analogous case with reversed potentials for n-type semiconductors
15
SLIDE 16
Metal-Oxide-SC Field-effect Transistor (MOSFET)
◮ Enhancement n-channel MOSFET: metal-p capacitor surrounded by n+ ◮ MOS inversion: generates an n channel at surface ◮ Comparison with n-JFET: existing channel suppressed by gate junction ◮ Analogous depletion n-MOSFET: replace p above with light n ◮ Flip n ↔ p and polarities ⇒ enhancement and depletion p-MOSFETs
16
SLIDE 17
MOSFET: gate response
◮ For VGS < Vth, n+ contacts separated by depletion layer ◮ No channel ⇒ ID = 0 irrespective of VDS ◮ One VGS > Vth, inversion layer forms an n-channel ◮ For low VDS, channel behaves like an Ohmic resistor
17
SLIDE 18
MOSFET: drain response
◮ Increasing VDS causes reduction in VGD ◮ Channel begins to narrow near drain; current starts to level off ◮ At VDS = V sat
DS = VGS − Vth, channel pinches off at drain end
◮ Beyond this potential, ID does not increase with increasing VDS
18
SLIDE 19
MOSFET: IV characteristics
◮ Saturation drain voltage V sat
DS = VGS − Vth
◮ Saturation drain current IDS = K(VGS − Vth)2(1 + λVDS) ◮ Coefficient K ∼ Cµe
2L2 , where C = MOS capacitance, L = channel length
◮ Coefficient λ due to Early effect (exactly like in BJT, JFET) ◮ Similar characteristics to JFET ⇒ similar amplifier circuits ◮ Switching: VGS > Vth ⇒ RDS small (on) vs VGS < Vth ⇒ RDS large (off) ◮ On-off ratio Roff
DS/Ron DS, switching time ∼ RC
19
SLIDE 20
Complementary MOS (CMOS) logic
◮ Complementary MOS: combine p and n-MOS transistors ◮ Inverter / NOT gate: Vin < Vth ⇒ Vout = Vdd, Vin > Vth ⇒ Vout = Vss ◮ Digital logic: for input 0 and 1, output 1 and 0 respectively ◮ NOR (NOT OR) gate: output 0 (NOT 1) if any input 1 ◮ NAND (NOT AND) gate: output 0 (NOT 1) if all inputs 1 ◮ Any logic or arithmetic operation using just three gates!
20
SLIDE 21
Arithmetic circuits
◮ XOR (exclusive OR) gate: output 1 if exactly one input 1 ◮ 1-bit adder: sum bit = XOR, carry bit = AND ◮ 8-bit adder: chain bit additions together ◮ N-bit adder: requires ∝ N log2 N gates ◮ N-bit multiplier: adder of N numbers with N-bits each
21
SLIDE 22
Example: Xeon Phi 7210
◮ 64 compute cores ◮ Each core: 8× 64-bit multipliers ◮ Net: 1012 64-bit math operations per second ◮ 8 × 109 CMOS transistors in 8 cm2 of Si!
22
SLIDE 23
Bistable latches (flip-flops)
◮ When R = S = 0: latch stores previous value ◮ Feedback loop between two inverters ◮ S = 1 sets value to 1, R = 1 resets it to 0 ◮ Volatile memory: data lost when circuit powered off ◮ Mechanism used in registers and static RAM ◮ Minimum 8 transistors / bit as shown above (low-density, high power)
23
SLIDE 24
Dynamic RAM
◮ Bit = whether capacitor is charged ◮ Transistor in off state: capacitor isolated; retains charge ◮ To read, transistor in specific row and column switched on ◮ Reading destroys state; must be written back ◮ State lost due to leakage ⇒ refresh circuitry ◮ Volatile: charge retention only ∼ 100 ms ◮ 1 transistor / bit: high-density, low power ◮ 8GB DDR4 memory: 8 × 109 transistors in < 10 cm2 Si
24
SLIDE 25