Ferroelectric Field Effect Ferroelectric Field Effect Transistors Transistors Reza M. Rad Rad Reza M. UMBC UMBC Based on pages 387- -403 of 403 of “ “Nanoelectronics Nanoelectronics and and Based on pages 387 Information Technology” ”, Rainer , Rainer Waser Waser Information Technology
Introduction Introduction � Ferroelectrics Ferroelectrics : dielectric crystals which : dielectric crystals which � show a spontaneous electric polarization show a spontaneous electric polarization and the direction of polarization can be and the direction of polarization can be reoriented by an external electric field reoriented by an external electric field � In ferroelectric memories, direction of In ferroelectric memories, direction of � spontaneous polarization is used to store spontaneous polarization is used to store digital bits digital bits
Introduction Introduction � Non Non- -volatile electrically volatile electrically switchable switchable data data � storage devices can be implemented storage devices can be implemented � Typically implemented as a capacitor Typically implemented as a capacitor � consisting of a thin ferroelectric film in consisting of a thin ferroelectric film in between two conductive electrodes between two conductive electrodes
Introduction Introduction � Voltage pulse applied to the cap Voltage pulse applied to the cap � determines the polarity (“ “0 0” ” or or “ “1 1” ”) ) determines the polarity ( � For readout another voltage pulse is For readout another voltage pulse is � applied that determines whether or not applied that determines whether or not polarization switched direction polarization switched direction � Read process is non Read process is non- -destructive destructive �
Introduction Introduction � Efforts focused on development of Efforts focused on development of � ferroelectric FETs FETs ferroelectric � Data read out in Data read out in FeFET FeFET in non in non- -destructive destructive � � FeFET FeFET has both memory and logic has both memory and logic � functions functions � FeFET FeFET is similar to is similar to MOSFETs MOSFETs, the gate , the gate � oxide is a ferroelectric material oxide is a ferroelectric material
Principles of FeFETs FeFETs Principles of � Ferroelectric memories are based on 1 Ferroelectric memories are based on 1 � (MOS) transistor– –1 capacitor (1T1C) 1 capacitor (1T1C) (MOS) transistor approach approach � Transistor is separated by a thick dielectric Transistor is separated by a thick dielectric � layer from ferroelectric cap layer from ferroelectric cap � Reliability issues exist in fabrication of Reliability issues exist in fabrication of � 1T1C cell 1T1C cell
Principles of FeFETs FeFETs Principles of � Figure (fig 1) shows the Figure (fig 1) shows the � conventional DRAM, 1T1C conventional DRAM, 1T1C ferroelectric cell and FeFET FeFET ferroelectric cell and
Principles of FeFETs FeFETs Principles of � Figure (fig 2) Figure (fig 2) � shows the layout shows the layout of a FeFET FeFET of a
Principles of FeFETs FeFETs Principles of � Figure (fig 3) shows the charge motion in a Figure (fig 3) shows the charge motion in a � FeFET during one cycle of operation during one cycle of operation FeFET
Principles of FeFETs FeFETs Principles of � Vg> Vg>Vc Vc : polarization vector P is directed : polarization vector P is directed � toward Si Si toward � Accumulation of electrons in channel, on state Accumulation of electrons in channel, on state � � Vg< Vg<- -Vc Vc : Pr is directed opposite, electrons are : Pr is directed opposite, electrons are � depleted depleted � Non Non- -destructive readout : sense the source destructive readout : sense the source � drain resistance drain resistance � FeFET FeFET memories: memories: - -non non- -volatile , volatile , - -non non- - � destructive readout , - - compact cell design compact cell design destructive readout ,
Principles of FeFETs FeFETs Principles of � Design structures for Design structures for FeFETs FeFETs and material and material � aspects aspects � As seen in the layout of As seen in the layout of FeFET FeFET, a stack of , a stack of � metal- -ferroelectric ferroelectric- -semiconductor is required semiconductor is required metal for FeFET FeFET for � Challenges in interfacing Challenges in interfacing Si Si and ferroelectrics: and ferroelectrics: � • Lattice mismatch must be as small as possible Lattice mismatch must be as small as possible • • Chemical reactions and intermixing should be Chemical reactions and intermixing should be • minimized minimized • Number of interface states should be less than Number of interface states should be less than • 12 eV -1 1 cm -2 2 10 12 eV - cm - 10 • Formation of low Formation of low- -k dielectrics should be avoided k dielectrics should be avoided • • Ferroelectric must form a pinhole free layer Ferroelectric must form a pinhole free layer •
Principles of FeFETs FeFETs Principles of � Only few Only few Perovskite Perovskite oxides are suitable for oxides are suitable for � growth on silicon growth on silicon � Alternative gate stack layouts and various Alternative gate stack layouts and various � buffer layer configurations have been buffer layer configurations have been developed: developed: • MFS : metal MFS : metal- -ferroelectric ferroelectric- -semiconductor semiconductor • • MFIS: metal MFIS: metal- -ferroelectric ferroelectric- -insulator insulator- -semiconductor semiconductor • • MFMIS : metal MFMIS : metal- -ferroelectric ferroelectric- -metal metal- -insulator insulator- - • semiconductor semiconductor • MF MF- -ABO3 : ferroelectric on a conductive oxide (no ABO3 : ferroelectric on a conductive oxide (no • silicon) silicon)
Principles of FeFETs FeFETs Principles of � Figure (fig 4) shows these alternatives Figure (fig 4) shows these alternatives �
Principles of FeFETs FeFETs Principles of � Ferroelectric directly on silicon Ferroelectric directly on silicon � � The intermixing from The intermixing from Si Si to to Perovskite Perovskite leads to the leads to the � degradation of the ferroelectric properties degradation of the ferroelectric properties � Buffer layer between ferroelectric and silicon Buffer layer between ferroelectric and silicon � � The effect of charge injection can be minimized by The effect of charge injection can be minimized by � employing an engineered buffer sandwiched between employing an engineered buffer sandwiched between the silicon and Perovskite Perovskite layer layer the silicon and � Buffer layer reduces the problem of intermixing silicon Buffer layer reduces the problem of intermixing silicon � and ferroelectric and ferroelectric � Gate oxide is comprised of two capacitors in series Gate oxide is comprised of two capacitors in series � � Buffer layer weakens the electric field across Buffer layer weakens the electric field across � ferroelectric ferroelectric
Principles of FeFETs FeFETs Principles of � Metal Metal- -ferroelectric ferroelectric- -metal gate structures metal gate structures � � MFMIS structure reduces the intermixing MFMIS structure reduces the intermixing � problems problems � However, it acts as a voltage divider However, it acts as a voltage divider � � Gate voltage is divided according to Gate voltage is divided according to � capacitance ratio of the MIS and MFM capacitance ratio of the MIS and MFM � Capacitance of MIS diode should be large Capacitance of MIS diode should be large � enough to allow the polarization reversal of enough to allow the polarization reversal of MFM MFM � Relatively large voltage necessary to switch Relatively large voltage necessary to switch � the ferroelectric capacitor (in case of SiO2 the ferroelectric capacitor (in case of SiO2 insulator) insulator)
Principles of FeFETs FeFETs Principles of � Meta Meta- -Ferroelectric on a conductive oxide Ferroelectric on a conductive oxide � � Source Source- -drain channel is replaced by a drain channel is replaced by a � conductive oxide conductive oxide � These have similar growth conditions as These have similar growth conditions as � ferroelectrics ferroelectrics � The aim is to modulate conductivity of the The aim is to modulate conductivity of the � conductive oxide by the polarization of conductive oxide by the polarization of ferroelectric ferroelectric
Electrical characterization of FeFETs FeFETs Electrical characterization of � For MFIS gate structure the drain current in linear For MFIS gate structure the drain current in linear � regime is given by: regime is given by: = − µ + − * I ( W / L ) [ P C ( V V )] V D h GS T SD = + * P PC /( C C ) B B Fe µ L : gate length , W : gate width , : effective hole mobility h P : polarizati on of ferroelect ric , C : gate capacitanc e per unit area � The drain conductance and The drain conductance and transconductance transconductance are given are given � by: by: = − µ + − * g ( W / L ) [ P C ( V V )] D h GS T = − µ g ( W / L ) CV m h SD
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