IEE5009 – Autumn 2012 Memory Systems Storage Class Memory Chiao-Ying, Huang Department of Electronics Engineering National Chiao Tung University saomyhunag@gmail.com Chiao-Ying, Huang 2012
Outline Issues for Traditional Memory System Disk Technology Trend Introduction to Storage Class Memory (SCM) Candidates of Storage Class Memory System Impact Conclusion Reference 2 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Issues for Traditional Memory System The performance gap between disks and the rest of the system, which is already five orders of magnitude, continues to widen rapidly. Critical computing applications are becoming more data-centric than compute-centric; therefore, disk has becoming more and more important in the advance computer system. In addition, the energy consumption, space usage and cost of disks are major obstacles to the development of extra-scale system capable of 10 18 operations per second. 3 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Disk Technology Trend Areal density of disk drives and its impact on cost ,capacity and power use are of interest nowadays. The growth rate of disk areal density was striking in the late 1990s and early 2000s, but then it slowed and stayed at 40% in the foreseeable future. CAGR: Compound Annual Growth Rate. Disk drives are also transforming from 3.5-inch to 2.5-inch for higher storage performance requirement. More disk drives can be used such that more I/O operations per second; therefore, performance increase. Likely that it will transit from 2.5-inch to 1.8-inch after 2015. 4 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Disk Technology Trend Performance: latency improvements are lagging bandwidth improvements throughout the computing industry, causing problems for applications dependent on latency most. Access time: drives spinning much faster than 15000 rpm within the next decade is not feasible, thus, the rotational latency of disks will stay at or above 2ms. 5 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Disk Technology Trend Power: it varies only when moving to a new track during normal system operation and it takes a long time to power up a disk drive for archival based system. Simply by adding the number of disk drives to compensate for bandwidth and latency limitation in enterprise storage servers will need millions of HDDs by 2020.These disks will consume most of the space and power budget. Also, scaling devices size no longer results in direct performance improvements, people seeks for changing in the memory-storage hierarchy. 6 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Introduction to Storage Class Memory SCM features: non-volatile, solid-state implementation (no moving part), short access time (DRAM like), low cost per bit (HDD like), better durability. SCM can be used as not only storage device but also memory. System target for SCM: mobiles and datacenter. The table below summarizes the essential specification of idea SCM. 7 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Introduction to Storage Class Memory Some materials can be sandwiched between two orthogonal planes of parallel conductors providing an wordline and bitline as a cell. Candidates of SCM: Flash and charge-trapping memory Still slow and poor write endurance. Ferroelectric RAM: Used today, but poor scalability. Magnetic RAM: Used today, but poor scaling. Magnetic Racetrack: Basic research, but very promising in long term. Phase – change RAM: Most promising now (scaling). Resistive RAM: Early development, promising. 8 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Introduction to Storage Class Memory Access time of an SCM chip is three to five orders of magnitude faster than a disk drive. Write endurance is the first challenge and SCM developers are striving for a write endurance 10 8 -10 12 writes per cell. A flash bit cell can be written10 4 – 10 5 times. DRAM chips will survive being written 10 15 times. Disk drives may survive being written 10 12 times. Wear-leveling schemes can ameliorate the write endurance problem as it is used for flash memory today. The second challenge is to scale cross-point memories down to a size that makes them cost competitive with disk drives. 9 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Introduction to Storage Class Memory Three techniques are expected to yield such memories (scale-down): 1. Three-dimensional (3D) integration of multiple layers of memory. 2. Multiple bits per cell using MLC techniques. 3. Sub-lithographic crossbar memory to go beyond the lithographic dimension. 3D Integration Sub-lithographic M bits/cell 10 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Flash and Charge-trapping Memory The gate has been redesigned to allow electrons to be placed (or removed) near the gate during a writing step. The presence (absence) of this charge shifts (restores) the threshold voltage of the transistor, allowing detection of the binary state of the memory cell. Flash attributes: nonvolatile, reprogrammable and erased electrically in less than a second. 11 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Flash and Charge-trapping Memory NAND flash: Arranged in series within small blocks, thus more compact than NOR flash. Write operation is quite slow per bit, and this very low current allows many bits to be written in parallel; therefore, result in reasonable write bandwidth. Slow random access makes it suited for applications requiring primarily block- based access, such as the storage of digital music, photos, and video. MLC concept is also used to make effective cell size per bit down to 2F 2 . “128Gb 3-Bit Per Cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate and 400Mbps Toggle Mode” has been proposed in ISSCC, 2012. NAND flash challenges: Shrinking the lithography pitch and device-to-device variations. Stringent data-retention problem for MLC sets a limit on the thickness of tunnel oxide of roughly 7nm. Scaling of floating gate beyond 40nm causes interference between adjacent memory devices.. 12 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Flash and Charge-trapping Memory Charge-trapping memory: Replace the floating gate with a charge-trapping layer, such as SONOS . Early SONOS memory exhibit better scalability and acceptable write and erase performance, but suffered from data retention issue. Recently, owing to high-K dielectric materials and metal gate, both erase and retention characteristic. By changing the sandwiched materials (ONO layer), it can obtain low leakage yet low programming current. Challenge for bot flash and charge-trapping memory: Charge loss issue, which is due to limited number of stored electrons available for MLC operation, gets worse with continued scaling of the cell. Other avenue to introduce traps: Nanocrystals. 13 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Ferroelectric RAM Misconception: ferroelectric crystals are ferromagnetic Ferroelectric materials switch in an electric field and are not affected by magnetic fields. Ferroelectric refers to similarity of the graph of charge plotted as a function of voltage to the hysteresis loop (BH curve) of ferromagnetic materials. Formed by sandwiching a ferroelectric material, Perovskites, between two metallic electrodes. The ferroelectric material has two states: the atom at the top, called up polarization. the atom at the bottom, called down polarization. 14 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Ferroelectric RAM The FeRAM is formed by a ferroelectric capacitor, an access transistor, a bitline, a plate line and a wordline. Its read/write operation is detailed in [18]. FeRAM’s advantages: high speed, low-power, rewritable, nonvolatile, larger capacity and the possible straightforward CMOS integration. Scaling the device area with smaller capacitor inherently leads to smaller signal levels. Thus, fabrication of FeRAM has moved from strapped device to stacked device to 3D device . One of the most commercially successful new NVM: Used in the Sony PlayStation** 2 system. Future prospect: Significant breakthrough in the integration of ultra -small cells using 3D ferroelectric capacitors without sacrificing reliability or memory performance. 15 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
Magnetic RAM MRAM is composed of transistors but it uses magnetic charges to store information instead of electrical charges. The cell consists of two ferromagnetic electrodes separated by a very thin insulating layer. One of the magnetic electrode is pinned, called fixed layer. The other electrode’s magnetic orientation can be altered, called free layer. The binary state of MRAM is determined by whether the orientation of the two layers are parallel or not. These relative magnetic orientations correspond to the binary memory states, either 0 or 1. 16 Chiao-Ying Huang NCTU IEE5009 Memory Systems 2012
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