IEE5009 Autumn 2012 Memory Systems Storage Class Memory - - PowerPoint PPT Presentation

Chiao-Ying, Huang 2012

IEE5009 –Autumn 2012 Memory Systems Storage Class Memory

Chiao-Ying, Huang Department of Electronics Engineering National Chiao Tung University saomyhunag@gmail.com

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Outline

Issues for Traditional Memory System Disk Technology Trend Introduction to Storage Class Memory (SCM) Candidates of Storage Class Memory System Impact Conclusion Reference

2

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Issues for Traditional Memory System

 The performance gap between disks and the rest of the system, which is already five orders of magnitude, continues to widen rapidly.  Critical computing applications are becoming more data-centric than compute-centric; therefore, disk has becoming more and more important in the advance computer system.  In addition, the energy consumption, space usage and cost of disks are major obstacles to the development of extra-scale system capable of 1018 operations per second.

3

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Disk Technology Trend

 Areal density of disk drives and its impact on cost ,capacity and power use are of interest nowadays.  The growth rate of disk areal density was striking in the late 1990s and early 2000s, but then it slowed and stayed at 40% in the foreseeable future.

 CAGR: Compound Annual Growth Rate.

 Disk drives are also transforming from 3.5-inch to 2.5-inch for higher storage performance requirement.

 More disk drives can be used such that more I/O operations per second; therefore, performance increase.  Likely that it will transit from 2.5-inch to 1.8-inch after 2015.

4

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Disk Technology Trend

 Performance: latency improvements are lagging bandwidth improvements throughout the computing industry, causing problems for applications dependent on latency most.  Access time: drives spinning much faster than 15000 rpm within the next decade is not feasible, thus, the rotational latency of disks will stay at or above 2ms.

5

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Disk Technology Trend

 Power: it varies only when moving to a new track during normal system operation and it takes a long time to power up a disk drive for archival based system.  Simply by adding the number of disk drives to compensate for bandwidth and latency limitation in enterprise storage servers will need millions of HDDs by 2020.These disks will consume most of the space and power budget.  Also, scaling devices size no longer results in direct performance improvements, people seeks for changing in the memory-storage hierarchy.

6

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Introduction to Storage Class Memory

 SCM features: non-volatile, solid-state implementation (no moving part), short access time (DRAM like), low cost per bit (HDD like), better durability.  SCM can be used as not only storage device but also memory.  System target for SCM: mobiles and datacenter.  The table below summarizes the essential specification of idea SCM.

7

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Introduction to Storage Class Memory

 Some materials can be sandwiched between two orthogonal planes

• f parallel conductors providing an wordline and bitline as a cell.

 Candidates of SCM:

 Flash and charge-trapping memory

• Still slow and poor write endurance.

 Ferroelectric RAM:

• Used today, but poor scalability.

 Magnetic RAM:

• Used today, but poor scaling.

 Magnetic Racetrack:

• Basic research, but very promising in long term.

 Phase–change RAM:

• Most promising now (scaling).

 Resistive RAM:

• Early development, promising.

8

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Introduction to Storage Class Memory

 Access time of an SCM chip is three to five orders of magnitude faster than a disk drive.  Write endurance is the first challenge and SCM developers are striving for a write endurance 108-1012 writes per cell.

 A flash bit cell can be written104–105 times.  DRAM chips will survive being written 1015 times.  Disk drives may survive being written 1012 times.

 Wear-leveling schemes can ameliorate the write endurance problem as it is used for flash memory today.  The second challenge is to scale cross-point memories down to a size that makes them cost competitive with disk drives.

9

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Introduction to Storage Class Memory

 Three techniques are expected to yield such memories (scale-down):

1. Three-dimensional (3D) integration of multiple layers of memory. 2. Multiple bits per cell using MLC techniques. 3. Sub-lithographic crossbar memory to go beyond the lithographic dimension.

10 3D Integration M bits/cell Sub-lithographic

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Flash and Charge-trapping Memory

 The gate has been redesigned to allow electrons to be placed (or removed) near the gate during a writing step.  The presence (absence) of this charge shifts (restores) the threshold voltage of the transistor, allowing detection of the binary state of the memory cell.  Flash attributes: nonvolatile, reprogrammable and erased electrically in less than a second.

11

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Flash and Charge-trapping Memory

 NAND flash:

 Arranged in series within small blocks, thus more compact than NOR flash.  Write operation is quite slow per bit, and this very low current allows many bits to be written in parallel; therefore, result in reasonable write bandwidth.  Slow random access makes it suited for applications requiring primarily block- based access, such as the storage of digital music, photos, and video.  MLC concept is also used to make effective cell size per bit down to 2F2.  “128Gb 3-Bit Per Cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate and 400Mbps Toggle Mode” has been proposed in ISSCC, 2012.

 NAND flash challenges:

 Shrinking the lithography pitch and device-to-device variations.  Stringent data-retention problem for MLC sets a limit on the thickness of tunnel oxide of roughly 7nm.  Scaling of floating gate beyond 40nm causes interference between adjacent memory devices..

12

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Flash and Charge-trapping Memory

 Charge-trapping memory:

 Replace the floating gate with a charge-trapping layer, such as SONOS .  Early SONOS memory exhibit better scalability and acceptable write and erase performance, but suffered from data retention issue.  Recently, owing to high-K dielectric materials and metal gate, both erase and retention characteristic.  By changing the sandwiched materials (ONO layer), it can obtain low leakage yet low programming current.

 Challenge for bot flash and charge-trapping memory:

 Charge loss issue, which is due to limited number of stored electrons available for MLC operation, gets worse with continued scaling of the cell.

 Other avenue to introduce traps:

 Nanocrystals.

13

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Ferroelectric RAM

 Misconception: ferroelectric crystals are ferromagnetic  Ferroelectric materials switch in an electric field and are not affected by magnetic fields.  Ferroelectric refers to similarity of the graph of charge plotted as a function of voltage to the hysteresis loop (BH curve) of ferromagnetic materials.  Formed by sandwiching a ferroelectric material, Perovskites, between two metallic electrodes.  The ferroelectric material has two states:

 the atom at the top, called up polarization.  the atom at the bottom, called down polarization.

14

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Ferroelectric RAM

 The FeRAM is formed by a ferroelectric capacitor, an access transistor, a bitline, a plate line and a wordline.

 Its read/write operation is detailed in [18].

 FeRAM’s advantages: high speed, low-power, rewritable, nonvolatile, larger capacity and the possible straightforward CMOS integration.  Scaling the device area with smaller capacitor inherently leads to smaller signal levels. Thus, fabrication of FeRAM has moved from strapped device to stacked device to 3D device.  One of the most commercially successful new NVM:

 Used in the Sony PlayStation** 2 system.

 Future prospect:

 Significant breakthrough in the integration of ultra-small cells using 3D ferroelectric capacitors without sacrificing reliability or memory performance.

15

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Magnetic RAM

 MRAM is composed of transistors but it uses magnetic charges to store information instead of electrical charges.  The cell consists of two ferromagnetic electrodes separated by a very thin insulating layer.

 One of the magnetic electrode is pinned, called fixed layer.  The other electrode’s magnetic orientation can be altered, called free layer.

 The binary state of MRAM is determined by whether the orientation

• f the two layers are parallel or not. These relative magnetic
• rientations correspond to the binary memory states, either 0 or 1.

16

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Magnetic RAM

 The advantages of MRAM:

 Fast write speed.  Straightforward placement above the silicon using the CMOS BEOL.  High endurance, as there is no known wear-out mechanism.

 The problems of MRAM:

 Poor scaling issues.  Write currents remain very high showing no decreasing sign as devices scales. These currents cause electron-migration of the wires, becoming a major failure mechanism.

 One of the emerging MRAM is magnetic racetrack, which has been invented by IBM.

17

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Magnetic Racetrack

 Store data in magnetic domain walls by building a magnetic racetrack in the third dimension.  A series of DWs can be moved at high speed along magnetic nanowires by using nanosecond-long spin-polarized current pulses.  The advantages of magnetic racetrack:

 Low cost per bit of magnetic disk drives.  High performance and reliability of conventional solid state memories.  It can store as 10 to 100 bits per point rather than single bit per cell.

 “Racetrack Memory - a high-performance, low-cost, non-volatile memory,” IEDM, 2011, has demonstrated the key components of the racetrack memory.

18

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Phase-change Memory

 PCRAM exploits the large resistivity contrast between amorphous and crystalline states in phase change materials. And this large resistivity contrast makes MLC operation readily attainable.

 The amorphous phase has high electrical resistivity.  The crystalline phase has low electrical resistivity.

19

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Phase-change Memory

 To SET the state of the PCRAM cell:

 Apply an electrical pulse that heats a significant portion of the cell above crystallization temperature.

 To RESET the state of the PCRAM cell:

 A large electrical current is applied and then abruptly cut off to melt-quench the phase change material element.

 By controlling the temperature and the duration of the heating, either phase can be obtained in a few tens of nanoseconds.  The advantages of PCRAM:

 High endurance and fast speed.  Inherent scaling of the PCRAM process beyond the 22nm node.

 The most important unknown for the success of PCRAM is whether the memory access devices (diode or transistor) in a dense array will be able to supply sufficient current to RESET the cell.

20

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

System Impact

 SCM can be used as:

 Traditional storage, which will not fully exploit the performance of SCM.  A new storage device connected via new interfaces, which is an important paradigm for emerging data-centric applications.  An excellent paging device, its high performance can restore the usefulness of virtual memory concept to high-performance computing.  Fast cache inside a storage controller for disks.

21

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

System Impact

 SCM reduces the gap between storage and memory and could be used for many tasks in the memory and storage hierarchy.

22

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Conclusion

 Disk drives cannot be used as the storage medium for reasons of insufficient performance, excessive power and data center floor space used.  SCM technology as described promises to provide an effective storage system and minimize the performance gap.  Write endurance and cost per bit are still the major issues for most of the emerging SCM.  There are some emerging SCMs are not discussed here, such as resistive RAM, organic and polymeric memory and so on.  If the full promise of SCM can be realized, we could witness the birth

• f the first truly universal memory, capable of supplanting everything

in the memory and storage hierarchy between L1 cache DRAM and magnetic tape.

23

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Reference



• G. E. Moore,”Cramming More Components onto Integrated Circuits” Proceedings of IEEE, vol. 86, no. 1, pp.82-85,

1988. 

• J. Gray and A. Reuter. Transaction Processing: Concepts and Techniques, Morgan Kaufmann Publishers, 1993.



• B. N. Kurdi, J. C. Scott, et al., “Overview of candidate device technologies for storage-class memory,” IBM Journal of

Research and Development, vol. 52, issue: 4.5, pp.449-464, July 2008.  S.K. Moore, “Multicore Is Bad News For Supercomputers,“  Available: http://Spectrum.ieee.org/. [Accessed Nov. 2008].  C.H. Lam, “Storage Class Memory,” Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2010. 

• M. Johnson et al., ‘‘512-Mb PROM with a Three-Dimensional Array of Diode/Antifuse Memory Cells,’’ Solid-State

Circuits, IEEE Journal of, vol. 38, no. 11, pp. 1920–1928, Nov. 2003. 

• B. Eitan er al., ‘‘Multilevel Flash Cells and Their Trade-offs,’’ Proceedings of the IEEE International Electron Devices

Meeting, San Francisco, CA, pp. 169–172, 1996. 

• K. Gopalakrishnan, et al., “The Micro to Nano Addressing Block (MNAB),” Proceedings of the IEEE International

Electron Devices Meeting, Washington, DC, pp. 471–474, 2005. 

• G. Campardo and R. Micheloni, “Special Issue on Flash Technology,” Proc. IEEE, vol. 91, no. 4, 483–488, 2003.



• Y. Li, et al. “128Gb 3-Bit Per Cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate and 400Mbps

Toggle Mode”, ISSCC Dig. Tech. Papers, pp. 436-437, Feb. 2012. 

• C. W. Oh, et al., “4-Bit Double SONOS Memories(DSMs) Using Single-Level and Multi-Level Cell Schemes,”

Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, pp. 1–4, 2006. 

• C. H. Lee, et al., “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-giga Bit Flash

Memories,” Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, pp. 26.5.1–26.5.4, 2003.

24

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Reference



• Z. L. Huo, et al., “Band Engineered Charge Trap Layer for Highly Reliable MLC Flash Memory,” Proceedings of the

IEEE Symposium on VLSI Technology, Kyoto, Japan, pp. 138–139, 2007. 

• R. Muralidhar, et al., “A 6 V Embedded 90 nm Silicon Nanocrystal Nonvolatile Memory,” Proceedings of the IEEE

International Electron Devices Meeting, Washington, DC, pp. 26.2.1–26.2.4, 2003. 

• T. Endoh, et al., “Novel Ultrahigh-Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT)

Structured Cell,” IEEE Trans. Elect. Dev. 50, No. 4, pp. 945–951, 2003. 

• H. Tanaka,M., et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”

Proceedings of the IEEE Symposium on VLSI Technology, Kyoto, Japan, pp. 14–15, 2007.  C.J. Chevaller, et al, “A 0.13um 64Mb Multi-Layered Conductive Metal-Oxide Memory,” ISSCC, paper 14.3, 2010.  Ramtron International Corporation. "F-RAM Technology Brief," [Online]. Available:https://www.google.com/search?q=f- ram+technology&ie=utf-8&oe=utf-8&aq=t&rls=org.mozilla:zh-TW:official&client=firefox-a [Accessed: Sept. 2007]. 

• K. Kim and S. Lee, “Integration of Lead Zirconium Titanate Thin Films for High Density Ferroelectric Random Access

Memory,” J. Appl. Phys. 100, no. 5, 051604, 2006. 

• L. Thomas, et al., “Racetrack Memory: a high-performance, low-cost, non-volatile memory based on magnetic domain

walls,” Electron Devices Meeting (IEDM), IEEE International, pp. 24.2.1-24.2.4, Dec. 2011. 

• S. Raoux, et al., “Phase-Change Random Access Memory: A Scalable Technology,” IBM J. of Res. and Dev., vol. 52,
• no. 4-5, pp. 465, 2008.



• S. Piramanayagam, T. Chong, “Phase Change Random Access Memory,” Developments in Data Storage: Materials

Perspective, Wiley-IEEE Press, pp. 277-296, 2012. 

• B. F. Freitas, W. W. Wilcke, “Storage-class memory: The next storage system technology,” IBM Journal of Research

and Development, vol. 52, issue: 4.5, pp.439-447, July 2008.

25

NCTU IEE5009 Memory Systems 2012 Chiao-Ying Huang

Thank you for your listening.

26