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IEE5009 Autumn 2012 Memory Systems Ternary Content Addressable Memory Chiao-Ying, Huang Department of Electronics Engineering National Chiao Tung University saomyhunag@gmail.com Chiao-Ying, Huang 2012 Outline Introduction Core

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Chiao-Ying, Huang 2012

IEE5009 –Autumn 2012 Memory Systems Ternary Content Addressable Memory

Chiao-Ying, Huang Department of Electronics Engineering National Chiao Tung University saomyhunag@gmail.com

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Introduction

Conceptual view of a CAM.

 Single cycle throughput high speed.  Popular in network routers.  IP4 vs. IP6 larger capacity CAMs.  Power consumption issue.  Leakage current in advanced technologies.  Conventional CAM search operation.

Priority encoder is used.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Introduction – cont.

Two types of CAM cells : Binary vs. Ternary

 Both can store 0 and 1 state.  Ternary CAMs have additional “X” state.

CAM cell = Storage + Comparison Circuit.

 Storage circuit is implemented by SRAM.  Comparison circuit is implemented in different manners corresponding to each cell types.

NOR type, NAND type, Hybrid type etc.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Core cell

NOR cell : Multiple cells are connected in parallel forming a word by shorting the ML together with adjacent cells.

 ML remains high in match state and discharge when miss.  The comparison circuit is a XNOR logic gate.  High search speed , high power consumption.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Core cell – cont.

NAND cell : Multiple cells are connected in series forming a word by joining the MLn and MLn+1.

 ML discharges to ground in match state and remains high in miss.  The comparison circuit is a XNOR logic gate.  Power efficient with the penalty of low speed.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Core cell – cont.

Ternary cell : stores an additional don’t care value.

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Ternary core cell for NOR - type cell Ternary core cell for NAND - type cell

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Core cell – cont.

Modified Ternary cell :

 Reducing leakage power in advanced technology.  Destroy the prefix data to reduce the LP when state is “X”.  Without performance penalty.  Two main part of leakage current:

Subthreshold leakage
Gate leakage

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Conventional TCAM cell components and the corresponding state table

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Core cell – cont.

Modified Ternary cell (cont.) :

 Proposed scheme : Dynamic Power Source (DPS)  Extension of power gated scheme.

No need of extra gated MOS saving area.
Can reduce subthreshold leakage current largely.

 Modified XOR logic to prevent short-circuit path in comparison circuit.

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DPSVDD Implementation DPSGND Implementation Conventional TCAM cell components

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Hybrid - type matchline structure

 Combine the performance advantages of the NOR-type CAM and the power efficiency of the NAND-type CAM.  With a marginal area overhead and largely reduces dynamic power and improves search performance.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Matchline sensing scheme

Conventional matchline sensing scheme:

 Power issue severe.

Low swing scheme:

 Reduce ML voltage swing reduce dynamic power.  Potentially increasing speed.  Challenge: no externally generated referenced voltage.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Matchline sensing scheme – cont.

Selective precharge scheme:

 A 144-bit word divided into 3-bit part and remaining 141-bit part.

Saves about 88% of the matchline power.
Worst case: all initial bits matched, thus eliminating any power saving.

Pipeline scheme:

 Extension of selective precharge scheme.  Drawbacks:

Increased latency and area overhead.

 Enable the use of hierarchical searchlines.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Matchline sensing scheme – cont.

Butterfly matchline scheme:

 Increasing parallelism of search operation obtains high speed.  XOR-based conditional keeper provides noise tolerant.  Interlaced pipeline connection reduces power consumption.

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Critical path

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Searchline sensing scheme

Conventional sensing scheme:

 Apply with precharge matchline high scheme.  Power consumption is big and searchline cap is large bad.

Eliminating searchline precharge scheme:

 For matchline precharged low scheme.  In typical case, 50% reduction in searchline power.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Searchline sensing scheme

Don’t care based Hierarchical searchline:

 Decrease the switching capacitances and switching activities.  No search time overhead.  Global-Searchline (GBL) vs. Local-Searchline ( LSL).

GBLs activate every cycle.
LSLs activate depending on don’t care cells.

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Outline

Introduction Core cell Hybrid - type matchline structure Matchline sensing scheme Searchline sensing scheme Conclusion Reference

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NCTU IEE5009 Memory Systems 2012 Chiao-Ying, Huang

Conclusion

Two basic CAM cells, NOR/NAND type. Differences between CAM and TCAM. Power saving techniques based on cell structure, matchline scheme, searchline scheme. Dynamic power reduction is not enough in advanced technology, leakage power reduction has become more and more important. 3D stacked TCAM is another research in the future.

 A Low-Power Monolithically Stacked 3D-TCAM, ISCAS, 2008

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Reference



H. J. Chao, “Next generation routers,” Proc. IEEE, vol. 90, no. 9, pp. 1518–1558, Sep. 2002.



K. Pagiamtzis A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: a tutorial and survey," IEEE Journal of Solid-State Circuits ,

vol.41, no.3, pp. 712- 727, March 2006 

K. J. Schultz, F. Shafai, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully parallel 25 MHz, 2.5-Mb CAM,” in IEEE Int. Solid-State Circuits Conf.

(ISSCC) Dig. Tech. Papers, 1998, pp. 332–333. 

S. R. Ramírez-Chávez, “Encoding don’t cares in static and dynamic content- addressable memories,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal

Process., vol. 39, no. 8, pp. 575–578, Aug. 1992. 

S. Choi, K. Sohn, M.-W. Lee, S. Kim, H.-M. Choi, D. Kim, U.-R. Cho, H.-G. Byun,Y.-S. Shin, and H.-J. Yoo, “A 0.7 fJ/bit/search, 2.2 ns search time hybrid type

TCAM architecture,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 498–499.  Yen-Jen Chang, “Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power,” in IEEE Trans. Circuits Syst. II, November 2010  Chao-Ching Wang, Jinn-Shyan Wang and Chingwei Yeh, "High-Speed and Low-Power Design Techniques for TCAM Macros," IEEE Journal of Solid-State Circuits , vol.43, no.2, pp.530-540, Feb. 2008  Yen-Jen Chang and Yuan-Hong Liao, "Hybrid-Type CAM Design for Both Power and Performance Efficiency," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.8, pp.965-974, Aug. 2008 

G. Kasai,Y. Takarabe, K. Furumi, and M.Yoneda, “200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect

circuits and bank selection scheme,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 387–390. 

C. A. Zukowski and S.-Y. Wang, “Use of selective precharge for low-power content-addressable memories,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol.

3, 1997, pp. 1788–1791. 

K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in Proc. IEEE Custom

Integrated Circuits Conf. (CICC), 2003, pp. 383–386.  Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu and Wei Hwang, "“Green” micro-architecture and circuit co-design for ternary content addressable memory," IEEE International Symposium on Circuits and Systems , vol., no., pp.3322-3325, 18-21 May 2008 

K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in Proc. IEEE Custom

Integrated Circuits Conf. (CICC), 2003, pp. 383–386.  Jian-Wei Zhang, Yi-Zheng Ye, Bin-Da Liu and Feng Guan, "Self-timed charge recycling search-line drivers in content-addressable memories," IEEE International Symposium on Circuits and Systems, vol., no., pp.3070-3073, 24-27 May 2009  A.R. Patwary, B.M. Geuskens and S.-L.L.Lu, "Low-power Ternary Content Addressable Memory (TCAM) array for network applications," International Conference on Communications, Circuits and Systems, vol., no., pp.322-325, 23-25 July 2009