IEE5008 – Autumn 2012 Memory Systems 3D Nand Flash Memory Pranav Arya Department of Electronics Engineering National Chiao Tung University pranav_arya7@yahoo.co.in Pranav Arya, 2012
Outline Introduction Planar Nand Flash Technology Limitations in 2D Nand 3D Integration Vertical Channel 3D Nand Memory Vertical Gate 3D Nand Memory Effects of Noise Conclusion Reference 2 Pranav Arya NCTU IEE5008 Memory Systems 2012
Introduction – Memory Technology Figure 1. Memory technology taxonomy [13] Source: M. Wang, Technology trends on 3D-Nand flash memory, Impact Taipei, 2011 3 Pranav Arya NCTU IEE5008 Memory Systems 2012
Nand Memory Scaling Sub 20nm possible. Sub 10nm? 12 13 14 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Figure 2. Nand memory scaling trend [13] 4 Pranav Arya NCTU IEE5008 Memory Systems 2012
Nand Flash Scaling Issues How much can we scale down the cell? Dielectric thickness – current leak, breakdown Data retention, endurance How many electrons in cell? Restricted MLC operation Few electrons below 10nm Cell operation Operating voltages Noise performance – cross talk 5 Pranav Arya NCTU IEE5008 Memory Systems 2012
Number of Eleectrons Figure 3. Number of electrons per logic level [13] 6 Pranav Arya NCTU IEE5008 Memory Systems 2012
3D I NTEGRATION T ECHNOLOGY Lateral scaling limited Scaling in vertical direction Ground Car Parking Lot Multi level Car Parking Lot 7 Pranav Arya NCTU IEE5008 Memory Systems 2012
3D Integration Options 3D stacking performance Cost effective? TSV technology Still expensive Nand flash memory specific technology 8 Pranav Arya NCTU IEE5008 Memory Systems 2012
3D Nand Flash Technology Vertical Channel Nand Flash Memory Bit Cost Scalable (BiCS) Nand Pipe-shaped Bit Cost Scalable (P-BiCS) Nand Vertical Stack Array Transistor (VSAT) Nand Terabit Cell Array Transistor (TCAT) Nand Vertical Gate Nand Flash Memory Vertical Gate Nand PN diode decoding Independent Double Gate Single Crystalline Stacked Array (STAR) Nand 9 Pranav Arya NCTU IEE5008 Memory Systems 2012
Bit Cost Scalable (BiCS) Nand Few constant number of critical lithography process steps Punch and Plug process Figure 5. (a)Bird eye view of BiCS Nand, (b) top down view [1]. 10 Pranav Arya NCTU IEE5008 Memory Systems 2012
Fabrication Process Lower select gate transistor, memory string and upper select gate transistor are fabricated individually. Gate material is P+ poly-Si. Holes for transistor channel or memory plug are punched through and LPCVD TEOS film or ONO films are deposited. The bottom of dielectric films are removed by RIE and plugged by amorphous Si. Arsenic is implanted and activated for drain and source of upper device. Edges of control gate are processed into stair-like structure by repeating of RIE and resist sliming. For minimizing disturb, whole stack of control gate and lower select line are etched to have a slit. Upper select gate is cut into line pattern to work as row address selector. Via hole and BL are processed on the array and peripheral circuit simultaneously. Figure 6. Fabrication steps [1] 11 Pranav Arya NCTU IEE5008 Memory Systems 2012
Pipe-shaped BiCS Nand BiCS limitations Small P/E window, read disturb and low data retention Doubtful for MLC operation Variation in voltage due to numerous cells on the same string cause LSG in heavily doped source makes diffusion profile difficult to control P-BiCS – pipe-like Nand string structure One terminal connected to BL and the other to SL 12 Pranav Arya NCTU IEE5008 Memory Systems 2012
Fabrication The first step is the PC formation. The next step is the deposition of the sacrificial films followed by memory- hole formation. For multiple layers multiple layers of memory films should be deposited. The SG transistors are formed after the fabrication of the Nand strings. After SG-hole formation the sacrificial films are removed. The removal of the sacrificial film leaves a U-pipe that connects two vertical Nand cells strings. Next the memory films are deposited and silicon deposition is done last Figure 7. Fabrication steps [2] 13 Pranav Arya NCTU IEE5008 Memory Systems 2012
Advantages over BiCS larger P/E window higher operating speed higher data retention of with no degradation after 10 years V th shift of less than 0.3 V Figure 8. P-BICS architecture [2] after 100k cycles of read operation at 7.5 V data retention and the immunity to read disturb are sufficient for MLC operation 14 Pranav Arya NCTU IEE5008 Memory Systems 2012
Vertical-Stacked Array Transistor (VSAT) BiCS and P-BiCS have stair like structure for peripherals Takes larger area VSAT removes the stair structure Figure 9. VSAT architecture, improvised base interconnect and staircase base [3] 15 Pranav Arya NCTU IEE5008 Memory Systems 2012
Fabrication A Si mesa is prepared by dry etching. Over this Si mesa multiple layers of gate electrodes and isolating films of poly-doped-silicon and nitride are deposited. The active regions are created through lithography followed by dry etching. Multiple WLs are patterned using KrF lithography followed by dry etching. All the gate electrodes are exposed on the same plane after a CMP process. The tunneling-oxide, charge-trapping-nitride, and control oxide films are deposited in turn on the active region, followed by a poly-silicon deposition process of the channel material. Finally, to isolate vertical strings, an etching process is carried out. Figure 10. Fabrication steps [3] 16 Pranav Arya NCTU IEE5008 Memory Systems 2012
Terabit Cell Array Transistor (TCAT) Metal gate structure Difficult etching metal/oxide multilayer simultaneously good erase speed, wider V th margin, and better retention GIDL erase of BiCS flash area overhead limited erase voltage Figure 11. TCAT architecture [4] 17 Pranav Arya NCTU IEE5008 Memory Systems 2012
Structural Changes Oxide/nitride multilayer stack sacrificial nitride layer is removed by wet removal process Line-type ‘W/L cut’ dry etched through the whole stack between the each row array of channel poly plug Line-type CSL formed by an implant through the ‘W/L cut’ W/L cut has no additional area penalty Metal gate lines for each row of poly plug. Gate replacement process implemented to achieve the metal gate SONOS structure 18 Pranav Arya NCTU IEE5008 Memory Systems 2012
Advantages over BiCS The channel poly plug connected to Si substrate Implementation of bulk erase operation without any major peripheral circuit changes. Smaller area overhead than BiCS flash 19 Pranav Arya NCTU IEE5008 Memory Systems 2012
Vertical Gate Nand Flash Memory Limitations of Vertical Channel Nand BiCS Nand flash has difficulty with WL interconnect, program disturbance, and channel resistance and they get worse as the number of WL between top BL and bottom CSL increases P-BiCS and TCAT have structures such that the channel current is conducted through a hole drilled through the layers in the vertical direction, and an additional WL-cut process must be applied to isolate the WL’s in the X direction. They have limited X pitch scalability due to the corresponding lithography overlay issue involved. The cell size of all vertical channel architectures is 6F 2 which is relatively large and does not correspond to the traditional planar Nand cell size As the number of layers increases, the read current inevitably degrades due to the increase in the length of the NAND string 20 Pranav Arya NCTU IEE5008 Memory Systems 2012
Vertical Gate Nand Architecture WL and BL are formed at the beginning of fabrication before cell array making interconnect between WL, BL and decoder easier Source and active body (V bb ) are electrically connected to CSL Enable body erase operation To perform erase operation a positive bias is applied to CSL Array schematic is similar to that of a planar Nand except SSL Common BL and common WL between multi-active layers to select data from a chosen layer out of multi-layers 21 Pranav Arya NCTU IEE5008 Memory Systems 2012
VG Nand Architecture Figure 12. Vertical gate Nand flash structure [5] 22 Pranav Arya NCTU IEE5008 Memory Systems 2012
Fabrication Integration scheme is based on simple patterning and plugging. BL with n+ poly-Si is fabricated first and then n+ poly-Si WL is formed on top of it. Multi-active layers with p-type poly-Si are formed with n-type ion implants for SSL layer selection Alternated inter-layer dielectrics are inserted between actives. Patterning is done on the multi-active layers Figure 13. Fabrication steps [5] and charge trap layers (ONO) are deposited over the patterned actives. Consecutively VG is formed and connected to WL. In the final step, vertical plugs of DC and Source-V bb are connected to BL and CSL after contact ion implants. N+ doped source and p-type active are electrically tied to CSL. 23 Pranav Arya NCTU IEE5008 Memory Systems 2012
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