Memory Systems Overview of the NAND Flash High- Speed Interfacing - PowerPoint PPT Presentation

IEE5008 – Autumn 2012 Memory Systems Overview of the NAND Flash High- Speed Interfacing and Controller Architecture Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University ninusyamit@gmail.com Chih-Yuan, Chang 2012 Nina, Mitiukhina 2012

Outline  Introduction  NAND Flash Background  NAND Flash Device Operation  NAND Flash Interface  NAND Flash Controller Functions  The ONFI Standard  Challenge of designing ONFI 3.0  Overview of Specific NAND Flash Controller Features  Conclusions  Reference Nina, Mitiukhina 2 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  NAND Flash enabling new markets Nina, Mitiukhina 3 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  NAND Flash pricing converges with HDD Nina, Mitiukhina 4 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  Price/performance positioning of different storage technologies  With the use of new sophisticated controllers, SSDs are getting closer to having best of both worlds – HDD costs and DRAM like performance Nina, Mitiukhina 5 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  Growing need for higher speed interfacing NAND Nina, Mitiukhina 6 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  Performance demand with a growth of storage interface Nina, Mitiukhina 7 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Introduction  Comparison of the number of bits for various memory storage arrays Nina, Mitiukhina 8 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  A little bit oh history: Toshiba’s Flash Memory chronicle Nina, Mitiukhina 9 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  Inherent limitations of NAND Flash Technology  Shipped with a number of bad blocks  Requires a serialized data interface  After experiencing multiple erase cycles, is wearing down; reliability degradation Nina, Mitiukhina 10 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  NAND SD vs. MMC Nina, Mitiukhina 11 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  NAND vs. NOR Nina, Mitiukhina 12 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  SLC vs. MLC  Complicated programming sequence Nina, Mitiukhina 13 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  SLC vs. MLC  Smaller memory window between neighbouring levels Nina, Mitiukhina 14 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  SLC vs. MLC  Degraded performance Nina, Mitiukhina 15 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Background  Data Organization Nina, Mitiukhina 16 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Device Operation  Block erase Nina, Mitiukhina 17 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Device Operation  Read operation  Page opening (~ 50us)  Data transfer (~ 20ns) Nina, Mitiukhina 18 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Device Operation  Write operation (part 1)  Incremental Step Pulse Programming plus verify scheme Nina, Mitiukhina 19 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Device Operation  Write sequence (part 2)  Shift data in shift registers  Issue command to program data into page Nina, Mitiukhina 20 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash device Operation  Interleave access Data bandwidth: Data transfer time + Page access time Nina, Mitiukhina 21 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Interface  NAND Flash Interface Evolution Nina, Mitiukhina 22 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Interface  SDR Asynchronous vs. Toggle Mode DDR  Faster Operation Speed  Less Power Consumption Asynchronous Interface with bi-directional DQS signal for reads and writes Nina, Mitiukhina 23 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Controller  Improves chip performance  Integrated controller  Smaller chip size  Cheaper cost  Dedicated (External) controller  Faster time to the market  More flexible design, large variety of compatible parts available on the market Nina, Mitiukhina 24 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Controller  Example: Flexible ONFI 2.2 compliant Controller for High Capacity MLC and High-Speed Data Transfer Nina, Mitiukhina 25 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Controller  Brief description of functional blocks:  DCU – Design Control Unit  Provide enable/disable signal to the DMA, SUI units, ECC module; provide control signal to NCU.  Execute boot sequence.  Interrupt controller.  SIU – Signalling Interface Unit  Coordinating interaction between the system interface and internal bus.  DMA – Direct Memory Access  Speeds up data transfer between a device on the system bus and a memory, decreasing system bus burden. Nina, Mitiukhina 26 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Controller  Brief description of functional blocks (part 2):  FIFO – 32 bit wide module  Data transferring between input module and NCU when command sequence is executed.  NCU – NAND Controller Unit  Responsible for generation of the device access sequences.  ECC – Error Correction unit  Correction code calculation.  PHY  Provides DDR data interface for the new high-speed devices. Nina, Mitiukhina 27 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

NAND Flash Controller  Core implementation results  ASIC  FPGA (Altera vs. Xylinx) Nina, Mitiukhina 28 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

ONFI Standard Recognizing the need for a common NAND interface, the ONFI Workgroup formed in May 2006 . Today the ecosystem is comprised of NAND Flash users and suppliers, including more than 100 leading technology companies. Nina, Mitiukhina 29 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

ONFI Standard  Major changes in ONFI revisions Nina, Mitiukhina 30 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  Released on March 15, 2011  NV-DDR2 interface enabling 400MT/s  Differential signaling for DQS and RE  DQS latency adjustment  External Vref  On-Die-Termination  Reduced input voltage levels (SSTL_18)  Vpp enablement Nina, Mitiukhina 31 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  MLC, SLC performance Nina, Mitiukhina 32 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  Data Interface Support Nina, Mitiukhina 33 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  Differential Signaling  Twice the noise immunity of the single ended signaling  Reduced sensitivity to SSO (simultaneously switching output noise)  Electromagnetic Interference reduction  Enhanced Common Mode Noise tolerance Nina, Mitiukhina 34 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  DQS latency adjustment  Pre-toggles DQS until valid DQS is stabilized  Tighter control of duty ratio  Adjustable latency – from 1 to 4 cycles Nina, Mitiukhina 35 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  Signalling Features (Vref + SSTL_18)  SSTL_18 Signaling  > 200 MT/s only supported with 1.8 Vcc  Industry Standard compatible  Higher speed, lower power consumption  External Vref  Reduce effects from external GND bounce  Enables tighter setups/holds due to controlled voltage reference Nina, Mitiukhina 36 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Challenge of designing ONFI 3.0  On-Die-Termination Challenge of designing ONFI 3.0 Nina, Mitiukhina 37 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Overview of Specific NAND Flash Controller Features  Error Correction  Bad Block Management  Wear Leveling strategies Nina, Mitiukhina 38 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Error Correction  ECC requirement range from 1-bit correction per 512 bytes to 40-bit per 1kbyte. , where N in the number of bits per block, E is the number of errors in a block and p is a bit error rate Nina, Mitiukhina 39 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Error Correction  Overview of relative ECC strength Nina, Mitiukhina 40 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012

Bad Block Management  Skip Block Method  Algorithm creates the bad block table, data is stored in the next good block, skipping the bad block.  Reserve Block Method  Bad blocks are not skipped but replaced by good blocks by redirecting FTL to a known free good block. Nina, Mitiukhina 41 Chih-Yuan, Chang NCTU IEE5008 Memory Systems 2012