Memory Systems Overview of the NAND Flash High- Speed Interfacing - - PowerPoint PPT Presentation

▶
memory systems
SMART_READER_LITE
LIVE PREVIEW

Memory Systems Overview of the NAND Flash High- Speed Interfacing - - PowerPoint PPT Presentation

Apr 15, 2023 378 likes •844 views

IEE5008 Autumn 2012 Memory Systems Overview of the NAND Flash High- Speed Interfacing and Controller Architecture Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University

slide-1
SLIDE 1

Chih-Yuan, Chang 2012 Nina, Mitiukhina 2012

IEE5008 –Autumn 2012 Memory Systems Overview of the NAND Flash High- Speed Interfacing and Controller Architecture

Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University ninusyamit@gmail.com

slide-2
SLIDE 2

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Outline

 Introduction  NAND Flash Background  NAND Flash Device Operation  NAND Flash Interface  NAND Flash Controller Functions  The ONFI Standard  Challenge of designing ONFI 3.0  Overview of Specific NAND Flash Controller Features  Conclusions  Reference

2

Nina, Mitiukhina

slide-3
SLIDE 3

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

NAND Flash enabling new markets

3

Nina, Mitiukhina

slide-4
SLIDE 4

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

NAND Flash pricing converges with HDD

4

Nina, Mitiukhina

slide-5
SLIDE 5

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

 Price/performance positioning of different storage technologies

 With the use of new sophisticated controllers, SSDs are getting closer to having best of both worlds – HDD costs and DRAM like performance

5

Nina, Mitiukhina

slide-6
SLIDE 6

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

Growing need for higher speed interfacing NAND

6

Nina, Mitiukhina

slide-7
SLIDE 7

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

 Performance demand with a growth of storage interface

7

Nina, Mitiukhina

slide-8
SLIDE 8

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

Comparison of the number of bits for various memory storage arrays

8

Nina, Mitiukhina

slide-9
SLIDE 9

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

 A little bit oh history: Toshiba’s Flash Memory chronicle

9

Nina, Mitiukhina

slide-10
SLIDE 10

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

Inherent limitations of NAND Flash Technology

Shipped with a number of bad blocks Requires a serialized data interface After experiencing multiple erase cycles, is wearing down; reliability degradation

10

Nina, Mitiukhina

slide-11
SLIDE 11

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

NAND SD vs. MMC

11

Nina, Mitiukhina

slide-12
SLIDE 12

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

NAND vs. NOR

12

Nina, Mitiukhina

slide-13
SLIDE 13

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

SLC vs. MLC

Complicated programming sequence

13

Nina, Mitiukhina

slide-14
SLIDE 14

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

SLC vs. MLC

Smaller memory window between neighbouring levels

14

Nina, Mitiukhina

slide-15
SLIDE 15

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

SLC vs. MLC

Degraded performance

15

Nina, Mitiukhina

slide-16
SLIDE 16

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Background

Data Organization

16

Nina, Mitiukhina

slide-17
SLIDE 17

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Device Operation

Block erase

17

Nina, Mitiukhina

slide-18
SLIDE 18

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Device Operation

Read operation

Page opening (~ 50us) Data transfer (~ 20ns)

18

Nina, Mitiukhina

slide-19
SLIDE 19

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Device Operation

Write operation (part 1)

 Incremental Step Pulse Programming plus verify scheme

19

Nina, Mitiukhina

slide-20
SLIDE 20

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Device Operation

Write sequence (part 2)

Shift data in shift registers Issue command to program data into page

20

Nina, Mitiukhina

slide-21
SLIDE 21

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash device Operation

Interleave access

Data bandwidth: Data transfer time + Page access time

21

Nina, Mitiukhina

slide-22
SLIDE 22

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Interface

NAND Flash Interface Evolution

22

Nina, Mitiukhina

slide-23
SLIDE 23

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Interface

SDR Asynchronous vs. Toggle Mode DDR

Faster Operation Speed Less Power Consumption

23 Asynchronous Interface with bi-directional DQS signal for reads and writes

Nina, Mitiukhina

slide-24
SLIDE 24

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Controller

Improves chip performance

Integrated controller

  • Smaller chip size
  • Cheaper cost

Dedicated (External) controller

  • Faster time to the market
  • More flexible design, large variety of compatible parts

available on the market

24

Nina, Mitiukhina

slide-25
SLIDE 25

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Controller

Example: Flexible ONFI 2.2 compliant Controller for High Capacity MLC and High-Speed Data Transfer

25

Nina, Mitiukhina

slide-26
SLIDE 26

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Controller

 Brief description of functional blocks:

 DCU – Design Control Unit

  • Provide enable/disable signal to the DMA, SUI units, ECC module; provide

control signal to NCU.

  • Execute boot sequence.
  • Interrupt controller.

 SIU – Signalling Interface Unit

  • Coordinating interaction between the system interface and internal bus.

 DMA – Direct Memory Access

  • Speeds up data transfer between a device on the system bus and a

memory, decreasing system bus burden.

26

Nina, Mitiukhina

slide-27
SLIDE 27

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Controller

 Brief description of functional blocks (part 2):

 FIFO – 32 bit wide module

  • Data transferring between input module and NCU when command

sequence is executed.

 NCU – NAND Controller Unit

  • Responsible for generation of the device access sequences.

 ECC – Error Correction unit

  • Correction code calculation.

 PHY

  • Provides DDR data interface for the new high-speed devices.

27

Nina, Mitiukhina

slide-28
SLIDE 28

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

NAND Flash Controller

Core implementation results

ASIC FPGA (Altera vs. Xylinx)

28

Nina, Mitiukhina

slide-29
SLIDE 29

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

ONFI Standard

29

Recognizing the need for a common NAND interface, the ONFI Workgroup formed in May 2006. Today the ecosystem is comprised of NAND Flash users and suppliers, including more than 100 leading technology companies.

Nina, Mitiukhina

slide-30
SLIDE 30

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

ONFI Standard

Major changes in ONFI revisions

30

Nina, Mitiukhina

slide-31
SLIDE 31

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

Released on March 15, 2011 NV-DDR2 interface enabling 400MT/s

  • Differential signaling for DQS and RE
  • DQS latency adjustment
  • External Vref
  • On-Die-Termination
  • Reduced input voltage levels (SSTL_18)

Vpp enablement

31

Nina, Mitiukhina

slide-32
SLIDE 32

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

MLC, SLC performance

32

Nina, Mitiukhina

slide-33
SLIDE 33

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

Data Interface Support

33

Nina, Mitiukhina

slide-34
SLIDE 34

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

Differential Signaling

Twice the noise immunity of the single ended signaling

  • Reduced sensitivity to SSO (simultaneously switching output noise)
  • Electromagnetic Interference reduction
  • Enhanced Common Mode Noise tolerance

34

Nina, Mitiukhina

slide-35
SLIDE 35

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

DQS latency adjustment

Pre-toggles DQS until valid DQS is stabilized

  • Tighter control of duty ratio
  • Adjustable latency – from 1 to 4 cycles

35

Nina, Mitiukhina

slide-36
SLIDE 36

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

Signalling Features (Vref + SSTL_18)

SSTL_18 Signaling

  • > 200 MT/s only supported with 1.8 Vcc
  • Industry Standard compatible
  • Higher speed, lower power consumption

External Vref

  • Reduce effects from external GND bounce
  • Enables tighter setups/holds due to controlled voltage

reference

36

Nina, Mitiukhina

slide-37
SLIDE 37

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Challenge of designing ONFI 3.0

On-Die-Termination

37 Challenge of designing ONFI 3.0

Nina, Mitiukhina

slide-38
SLIDE 38

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Overview of Specific NAND Flash Controller Features

Error Correction Bad Block Management Wear Leveling strategies

38

Nina, Mitiukhina

slide-39
SLIDE 39

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Error Correction

ECC requirement range from 1-bit correction per 512 bytes to 40-bit per 1kbyte.

39 , where N in the number of bits per block, E is the number of errors in a block and p is a bit error rate

Nina, Mitiukhina

slide-40
SLIDE 40

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Error Correction

Overview of relative ECC strength

40

Nina, Mitiukhina

slide-41
SLIDE 41

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Bad Block Management

Skip Block Method

Algorithm creates the bad block table, data is stored in the next good block, skipping the bad block.

Reserve Block Method

Bad blocks are not skipped but replaced by good blocks by redirecting FTL to a known free good block.

41

Nina, Mitiukhina

slide-42
SLIDE 42

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Wear Leveling

Controller maintains the lookup table to translate PBA to LBA used by the host

42 Wear-leveling methods: 1) Dynamic:  Write to the available erased block with the lowest erase count. 2) Static:  Select the available target block with the lowest overall erase count , erase the block if necessary, write new data to the block.

Nina, Mitiukhina

slide-43
SLIDE 43

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Wear Leveling

Static vs. Dynamic

43

Nina, Mitiukhina

slide-44
SLIDE 44

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Conclusions

 NAND Flash benefits include high storage density, low cost and low power requirements, however inherent limitations of the technology are severe and require careful controller design.  A well designed controller delivers the maximum bandwidth of the NAND Flash device, whereas poorly designed one only reduces system performance.  New generation high-performance interfacing NAND Flash based SSD with integrated controller unit can face growing industry demands.

44

Nina, Mitiukhina

slide-45
SLIDE 45

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

References

45

 [1] R. Micheloni, L. Crippa, and A. Marelli. Inside NAND Flash Memories. Springer, Chapter 7, 2010  [2] W. Doug (2006, 06) An overwiev of NAND Flash Memory controllers. LinuxDevices[eWeek] Available: http://www.linuxfordevices.com/c/a/Linux-For-Devices-Articles/An-overview-of-NAND-Flash-memory- controllers/  [3] NAND Flash White Paper, Eureka Technology Inc., los Altos, 2012. Available: http://www.eurekatech.com/scripts/mymail.pl  [4] W. Doug (2012, 10) Flash Technology: 200-400Mbps and Beyond. Available: http://www.jedec.org/sites/default/files/doug_wong.pdf  [5] T. Grunzke (2011, 07) ONFI 3.0 Enabling 400 MT/s. Available: http://extmedia.micron.com/webmedia/onfi3/onfi30.html  [6] K. Schurman (2011, 01) Toggle Mode NAND Flash. White paper [Hard hat area] Available: http://www.computerpoweruser.com/digitalissues/computerpoweruser/CP____1101__/44.html  [7] E. Deal (2009, 06) Trends in NAND Flash Memory Error Correction. Available: http://www.cyclicdesign.com/index.php/ecc-trends-in-nand-flash  [8] Bad Block Management in NAND Flash Memory, Micron Technology Inc., Boise, 2011  [9] Wear –Leveling Techniques in NAND Flash Devices, Micron Technology Inc., Boise, 2008  [10] NAND Flash Memory Controller IP Core, CAST Inc., Woodcliff Lake, 2011

Nina, Mitiukhina