Program Interference in MLC NAND Flash Memory: Characterization, - - PowerPoint PPT Presentation

Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation

Yu Cai1 Onur Mutlu1 Erich F. Haratsch2 Ken Mai1

1 Carnegie Mellon University 2 LSI Corporation

Flash Challenges: Reliability and Endurance

• E. Grochowski et al., “Future technology challenges for NAND flash and HDD products”,

Flash Memory Summit 2012

§ P/E cycles (required) § P/E cycles (provided) A few thousand Writing the full capacity

• f the drive

10 times per day for 5 years (STEC) > 50k P/E cycles

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NAND Flash Memory is Increasingly Noisy

Noisy NAND Write Read

3

Future NAND Flash-based Storage Architecture

Memory Signal Processing Error Correction

Raw Bit Error Rate Uncorrectable BER < 10-15

Noisy

High Lower

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Model NAND Flash as a digital communication channel Design efficient reliability mechanisms based on the model Our Goals:

NAND Flash Channel Model

Noisy NAND Write (Tx Information) Read (Rx Information)

Simplified NAND Flash channel model based on dominant errors

§ Erase operation § Program page operation § Neighbor page program § Retention

Cell-to-Cell Interference Time Variant Retention Additive White Gaussian Noise

Write Read

Cai et al., “Threshold voltage distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013 Cai et al., “Flash Correct-and-Refresh: Retention-aware error management for increased flash memory lifetime”, ICCD 2012

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Outline

n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference

q Read Reference Voltage Prediction

n Conclusions 6

How Current Flash Cells are Programmed

n Programming 2-bit MLC NAND flash memory in two steps 7 Vth

ER (11) LSB Program

Vth

ER (11) Temp (0x) MSB Program

Vth

ER (11) P1 (10) P2 (00) P3 (01)

1 1 1

Basics of Program Interference

n Traditional model of victim cell threshold voltage changes

when neighbor cells are programmed

Victim Cell WL<0> WL<1> WL<2>

(n,j)

(n+1,j-1) (n+1,j) (n+1,j+1) LSB:0 LSB:1 MSB:2 LSB:3 MSB:4 MSB:6 (n-1,j-1) (n-1,j) (n-1,j+1)

∆Vx ∆Vx ∆Vy ∆Vxy ∆Vxy ∆Vxy ∆Vxy ∆Vy

total xy xy y y x x victim

C V C V C V C V / ) 2 2 ( Δ + Δ + Δ = Δ

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Previous Work Summary

n No previous work experimentally characterized and

modeled threshold voltage distributions under program interference

n Previous modeling work

q Assumes linear correlation between the program interference

induced threshold voltage change of the victim cell and the threshold voltage changes of the aggressor cells

q Coupling capacitance and total capacitance of each flash cell

are the key coefficients of the model, which are process and design dependent random variables

q Their exact capacitance values are difficult to determine q Previously proposed model cannot be realistically applied in

flash controller

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Outline

n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference

q Read Reference Voltage Prediction

n Conclusions 10

Characterization Hardware Platform

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Cai et al., “FPGA-Based Solid-State Drive Prototyping Platform”, FCCM 2011

Characterization Studies

n Bitline to bitline program interference n Wordline to wordline program interference

q Program in page order q Program out of page order

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Bitline to Bitline Program Interference

n Vth distributions of victim cells under 16 ( 4 x 4) different neighbor values

{L, R} almost overlap

n Bitline to bitline program interferences are small

P1 State P2 State P3 State

Wordline ( N ) Wordline ( N+1 ) Wordline ( N-1 )

Victim Cell

X L R

L= { P0, P1, P2, P3 } R= { P0, P1, P2, P3 }

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WL to WL Interference with In-Page-Order Programming

Victim Word-line

Wordline ( N+1 ) Wordline ( N ) Wordline ( N-1 )

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n

Program interference increases the threshold voltage of victim cells and causes threshold voltage distributions shift to the right and become wider

n

Program interference depends on the locations of aggressor cells in a block

q

Direct neighbor wordline program interference is the dominant source of interference

q

Neighbor bitline and far-neighbor wordline interference are orders of magnitude lower

WL to WL Interference with Out-of-Page-Order Programming

Victim Word-line

Wordline ( N+1 ) Wordline ( N ) Wordline ( N-1 )

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n

The amount of program interference depends on the programming order of pages in a block

q

In-page-order programming likely causes the least amount of interference

q

Out-of-page-order programming causes much more interference

Comparison under Various Program Interference

n Signal-to-noise ratio comparison

Out-of-page-order Programming

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Data Value Dependence of Program Interference

20 40 60 80 aggressor ¡<11> aggressor<10> aggressor<00> aggressor ¡<01> Victim ¡Vth ¡Increase

MSB ¡Page ¡programmed ¡in ¡aggressor ¡cell

Victim ¡<10> Victim ¡<00> Victim ¡<01>

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n

The amount of program interference depends on the values of both the aggressor cells and the victim cells

Outline

n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference

q Read Reference Voltage Prediction

n Conclusions 18

n Feature extraction for Vth changes based on characterization

q Threshold voltage changes on aggressor cell q Original state of victim cell

n Enhanced linear regression model n Maximum likelihood estimation of the model coefficients

Linear Regression Model

∑ ∑

+ − = = + =

+ Δ = Δ

K j K j y M n n x before victim neighbor victim

j n V y x V y x j n V

1

) , ( ) , ( ) , ( ) , ( α α

ε α + = X Y

(vector expression)

) ( min arg

1 2 2

α λ α

α

+ − × Y X

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Model Coefficient Analysis

n Direct above cell dominance n Direct diagonal neighbor second n Far neighbor interference exists n Victim cell’s Vth has negative affect 20

Model Accuracy Evaluation

21 Ideal if no interference

(x,y)=(measured before interference, measured after interference)

Ideal if prediction is 100% accurate

(x,y)=(measured before interference, predicted with model)

With Systematic Deviation Without Systematic Deviation

Distribution of Program Interference Noise

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n Program interference noise follows multi-modal Gaussian-mixture

distribution

Program Interference vs P/E Cycles

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n Program interference noise distribution does not change significantly

with P/E cycles

Outline

n Background on Program Interference n Characterization of Program Interference n Modeling and Predicting Program Interference n Mitigation of Program Interference

q Read Reference Voltage Prediction

n Conclusions 24

Optimum Read Reference for Flash Memory

n Read reference voltage can affect the raw bit error rate n There exists an optimal read reference voltage

q Predictable if the statistics (i.e. mean, variance) of threshold

voltage distributions are characterized and modeled

Vth

f(x) g(x) v0 v1 vref

∫ ∫

∞ − +∞

+ =

ref ref

v v

dx x g dx x f BER ) ( ) ( 1

∫ ∫

∞ − +∞

+ =

ref ref

v v

dx x g dx x f BER

' '

) ( ) ( 2

Vth

f(x) g(x) v’ref v0 v1

State-A State-A State-B State-B

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Optimum Read Reference Voltage Prediction

n Learning function (periodically, every ~1k P/E cycles)

q

Program known data pattern and test Vth

q

Program aggressor neighbor cells and test victim Vth after interference

n Optimum read reference voltage prediction

q Default read reference voltage + Program interference noise mean

Evaluation Results

n Read reference voltage prediction can reduce raw BER and

increase the P/E cycle lifetime

32k-bit BCH Code (acceptable BER = 2x10-3) 30% lifetime improvement Raw bit error rate

No read reference voltage prediction With read reference voltage prediction

Outline

n Background of Program Interference n Program Interference Characterization n Modeling and Predicting Program Interference n Read Reference Voltage Prediction to Mitigate Program

Interference

n Conclusions 28

Key Findings and Contributions

n Methodology: Extensive experimentation with real 2Y-nm

MLC NAND Flash chips

n Amount of program interference is dependent on

q Location of cells (programmed and victim) q Data values of cells (programmed and victim) q Programming order of pages

n Our new model can predict the amount of program

interference with 96.8% prediction accuracy

n Our new read reference voltage prediction technique can

improve flash lifetime by 30%

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Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation

Yu Cai1 Onur Mutlu1 Erich F. Haratsch2 Ken Mai1

1 Carnegie Mellon University 2 LSI Corporation