IEE5008 Autumn 2012 Memory Systems Quad Data Rate SRAM for the - - PowerPoint PPT Presentation

Chih-Yuan, Chang 2012

IEE5008 –Autumn 2012 Memory Systems Quad Data Rate SRAM for the High-Throughput Communication Systems

Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University ninusyamit@gmail.com

Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Outline

 Introduction  Functional Description  Controller Function  System-Level Issues  Impact of the Device Scaling on System Performance  Applications  Conclusion  Reference

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Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Introduction

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QDR SRAMs are a family of SRAMs with separate Inputs and Outputs that each operate at Double Data Rates. Demand is growing rapidly for memories optimized for high bandwidth. The relentlessly expanding amount of information that travels over the Internet is creating the need for more and faster systems capable of routing and switching data across the globe. Higher-bandwidth memory is a requirement for these systems, and the QDR standard is specifically designed to address this need. Devices are designed to greatly increase memory bandwidth compared to existing SRAM solutions in applications such as switches and routers, and will typically be used for look-up tables, linked lists and controller buffer memory.

To the right  SRAM Memory suited for networking architecture performance comparison. QDR SRAM devices are compared against

• ther SRAM families such as double data

rate (DDR), zero-bus turnaround (ZBT), and SyncBurst. Compasiron assumes 125 MHz clock speed. Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

QDR Evolution

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Introduction

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

QDR Consortium. Milestones.

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Introduction

In 1999, the QDR SRAM Co-Development Team was created to define a new family of SRAM architectures for high-performance communications applications. Participating companies work closely together to ensure multiple sources for the new QDR SRAMs by developing pin- and function-compatible products. 1999 – 1) QDR-I specifications released; 2) Cypress, IDT and Micron team to provide new QDR SRAM architecture. 2001 – 1) JEDEC approves QDR-I; 2) QDR-I 9Mb sampled; 3) NEC, Samsung, Hitachi joins QRD consortium 4) QDR-ll specifications released 5) QDR-ll 18Mb sampled 2002 - 1) JEDEC approves QDR-II family of high-speed SRAM products 2) NEC Electronics ships QDR-II DDR-II family of high-speed SRAM products 3) Samsung leads next-generation networking with industry's first 36Mb QDR-ll SRAM 2006 - 1) QDR-ll+ and DDR-l SRAM specifications released 2) ODT(On Die Termination) feature made available in QDR-II+ products 3) QDR-II+ maximum frequency increased to 550MHz 2011 - QDR-ll+ Xtreme specifications released Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

QDR Product Family

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Introduction

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Functional Description

7 1) Separate write data (D) and read data (Q) ports that support simultaneous reads and writes and allow back-to-back transactions without the contention issues that can occur when using a single bidirectional data bus. 2) A shared address bus that alternately carries the read and write addresses. 3) A memory core made up of multiple SRAM arrays, permitting double data rate (DDR) access and a transfer rate of up to four words on every cycle.

QDR SRAM distinctive features:

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Functional Description

Example: burst-of-2 architecture

Signal Type Signal Name Description Clock

• utput

K, Kn Clock inputs to QDR SRAM. K_FB_OUT Is fed back to the controller as K_FB_IN to imitate the data flight times to and from QDR SRAM device. Clock input K_FB_IN Used by controller to generate READ_CLK for clocking in data. Control

• utput

RPSn Active-low read port select signal, sampled on the rising edge of K. WPSn Active-low write port select signal, sampled on the rising edge of K. BWSn[1..0] Active-low byte write select signal, sampled on the rising edge of K. Addres s

• utput

A[17..0] QDR SRAM’s address signals. Address inputs are sampled on the rising edge of K for reads and on the rising edge of Kn for writes. Data input D[17..0] Read data output from QDR SRAM. Data

• utput

Q[17..0] Write data input to the QDR SRAM.

Table 1. QDR SRAM Device Interface Signals Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

 Present Interface Signals

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Functional Description

Clock Signals Two pairs of clocks: K and Kn, and C and Cn. In dual-clock mode, K/Kn clocks are used for write accesses and the C/Cn clocks for read accesses. Device can also be set to the single- clock mode, where the K and Kn clocks are used for both reads and writes (C/Cn tied to VDD). Control Signals QDR SRAM devices use two control signals, write port select (WPSn) and read port select (RPSn), to control write and read operations, respectively. A third control signal, byte write select (BWSn), writes only one byte of data at a time, if necessary. Address Signals QDR SRAM devices use one address bus (A) for both read and write addresses. Data Signals QDR SRAM devices use two unidirectional data buses, one for writes (D) and one for reads (Q).

Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Functional Description

 QDR SRAM Functionality

QDR SRAM devices have a two-word or four-word burst capability. “Burst” : number of data words that are read or written on a single access. Burst-of-2 operation supports two-word data transfer on all write and read

• transactions. Requires a relatively simple controller implementation.

Burst-of-4 supports four-word data transfers on all write and read; address bus activity is reduced, more complicated interfacing with controller circuitry is needed. Note on Read/Write cycle: Independent read and write data paths, along with the cycle-shared address bus, allow read and write operations to occur in the same clock cycle. Performing concurrent reads and writes does not change the functionality of either transaction. If a read request occurs simultaneously with a write request at the same address, the data on D is forwarded to Q; therefore, latency is not required to access valid data.

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Functional Description

 Burst-of-2 Timing Diagram

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Functional Description

 Burst-of-4 Timing Diagram

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Controller Function

Example: Altera APEX 20KE

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Table 2. Example of the User Interface Signals

Signal Type Signal Name Description Clock

• utput

K, Kn Clock inputs to QDR SRAM. K_FB_OUT Is fed back to the controller as K_FB_IN to imitate the data flight times to and from QDR SRAM device. Clock input K_FB_IN Used by controller to generate READ_CLK for clocking in data. Control

• utput

RPSn Active-low read port select signal, sampled on the rising edge of K. WPSn Active-low write port select signal, sampled on the rising edge of K. BWSn[1..0] Active-low byte write select signal, sampled on the rising edge of K. Addres s

• utput

A[17..0] QDR SRAM’s address signals. Address inputs are sampled on the rising edge of K for reads and on the rising edge of Kn for writes. Data input D[17..0] Read data output from QDR SRAM. Data

• utput

Q[17..0] Write data input to the QDR SRAM.

Table 1. QDR SRAM Device Interface Signals Note: Controller read and write data path are independent thus it can perform reads and writes together or separately. Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Controller Function

Write cycle waveform (burst-of-2)

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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Read cycle waveform (burst-of-2)

Controller Function

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

System-Level Issues

High-Speed Transceiver Logic I/O Pins (HSTL I/O)

16 Circuit board layout affects signal integrity. Transmission line effects will affect signals even on short trace runs at the high

• speeds. Trace length and geometry are critical to maintaining signal integrity and

ensuring an error free system operation. To control reflections, the impedance of integrated circuit output pad drivers must be matched to the impedance of the transmission lines to which the pads are

• connected. HSTL (high-speed transceiver logic) controlled impedance I/O pads use

an on-chip impedance matching network that compensates for PVT variations. The QDR SRAM device interface requires the use o the HSTL I/O standard.

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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System-Level Issues

Clock Generation

1) INCLK – Input clock; 2) WRITE_CLK and WRITE_CLK_90 – controller clocks 1) K and Kn – QDR SRAM clocks 2) K_FB_IN and K_FB_OUT – Controller feedback clock 1) READ_CLK – Read data capture clock. Note: All L1 traces should be of equal length, all L2 traces should be of equal length as well. Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Timing: Write Cycle

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System-Level Issues

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

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System-Level Issues

Timing: Read Cycle

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Impact of the Device Scaling

65nm and 90nm Design Rule Comparison

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QDR II QDR II+ Frequency (Burst-of-4) 65nm 333 MHz 550 MHz 90nm 300 MHz 450 MHz Bandwidth (Burst-of-4) 65nm 48 Gbps 80 Gbps 90nm 44 Gbps 64 Gbps Idd - Active Current (Burst-of-4) 65nm 850mA 1310 mA 90nm 1040 mA 1475 mA Iddq – I/O Switching Current (Burst-of-4) 65nm 90mA 150 mA 90nm 80mA 120 mA Frequency (Burst-of-2) 65nm 333 MHz 333 MHz 90nm 300 MHz 300 MHz Bandwidth (Burst-of-2) 65nm 48 Gbps 48 Gbps 90nm 44 Gbps 44 Gbps Idd - Active Surrent (Burst-of-2) 65nm 990 mA 990 mA 90nm 1215 mA 1150 mA Iddq – I/O Switching Current (Burst-of-2) 65nm 90 mA 90 mA 90nm 80 mA 80 mA Input/Output Capacitance 65nm 4pF/4pF 4pF/4pF 90nm 5.5pF/6pF 5.5pF/7pF VDD (Core) 1.8V +/- 0.1V

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Routers and Switches

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Applications

Routers and Switches are devices that forward data packets across computer networks. Routers perform the data "traffic directing" functions on the Internet.

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Applications

22 QDR SRAMs are used in the Data Plane memory of Line Cards in edge and core routers for assisting the Network Processor and Traffic Manager in performing activities such as Statistics Measurements, Packet Buffering, Flow State Control, and Traffic Scheduling.

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

 Packet Buffer: Each line card on the router has an ingress buffer (or input port) and egress buffer (or output port). The input port or ingress buffer is the point of attachment for the physical link and point of entry for incoming packets. The output port or egress buffer stores packets and schedules them to dispatch to the switch fabric. The higher the line rate, the greater the needs of the packet buffer. QDR SRAMs can help address packet buffer applications, where customers use head/tail caching to complement DRAM.  Forwarding Information Base (FIB) Look Up Table: The FIB table stores the potential destination addresses of the next hop in the route. The look up is an iterative process and therefore involves multiple accesses to the memory. Each packet of data will require between 4 and 8 random accesses to the memory. Therefore, the QDR SRAMs are the memory of choice for table look up applications.  Packet classification or Access Control Limitation (ACL): This is a processing step to examine the characteristics of the incoming packets and make decisions on whether or not to allow the packet through. Once the packet has been classified or policed it is temporarily stored in a buffer subsystem for scheduling. QDR SRAMs can be used for ACL if algorithmic search is used instead of random search.

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Applications

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

 Scheduling: Scheduling is the process of deciding when to send a packet onto the switch

• fabric. Packets are grouped into several classes, each of which relate to a tiered service
• ffering. Typically the scheduling application requires 1R +1W per packet, and therefore is

less demanding in terms of RTR. For 100Gbps line card rates, scheduling can be serviced by QDR SRAMs.  Statistics & Flow States: Routers maintain statistics on a per packet and per flow basis. This is accomplished in the form of counters (up to 6 for each application). The counters are used to store information on prefix, flows, and packet classification. Hence counters have to be high performance memories that can accommodate multiple R/M/W operations in a second. Flow/State counters share the same memory foot print as that of statistics counters. QDR SRAMs in a line a card can be shared for Statistics and Flow/States.

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Applications

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NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Comparison of RTR Performance

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Applications

Random Transaction Rate is the number of fully random memory accesses that can be performed on the

• memory. Simply stated it is the rate at which random data can be addressed. This metric is independent of

the number of bits being accessed. RTR would be measured in million transactions per second or MT/s. Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

Conclusion

 QDR SRAM devices were designed for high-bandwidth communications applications and

• utperform other memory devices by up to four times in networking.

 Proper analysis of timing components is essential to ensure that the system works reliably and with the requested performance.  When undergoing scaling QDR SRAM performance improves. It shows faster operating frequencies, less power consumption, lower input and output capacitances, better signal integrity.  QDR SRAMs are used in the Data Plane memory of Line Cards in edge and core routers for assisting the Network Processor and Traffic Manager in performing activities such as Statistics Measurements, Packet Buffering, Flow State Control, and Traffic Scheduling. 26

Nina Mitiukhina 2012

NCTU IEE5008 Memory Systems 2012 Chih-Yuan, Chang

References

 B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems - Cache, DRAM, Disk. Elsevier, Chapter 1, 2008  A. Chakrapani (2010, 02) QDR SRAM and RLDRAM: A Comparative Analysis. Network Systems Design Line [EE Times]  AN-349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices, Altera corp., San Jose, 2004. AN-133: QDR SRAM Controller Function, Altera corp., San Jose, 2000.  Kang Li, “Optimization of QDR SRAM Controller in Network Processor,” in Proc. 2011 Fourth International Symp. On Computational Intelligence and Design, Baoding, 2011, pp. 371-374  AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide, Cypress Semiconductor Corp., San Jose, 2012.  J. Nayar (2012, 10) Advantages of 65 nm Technology over 90 nm Technology QDR Family of SRAMs.  Selecting the Right High-Speed Memory Technology for Your System, Altera Corp., San Jose, 2008

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