The New Standard / SigmaDDR-IIIe SigmaQuad-IIIe Quad Data Rate, - - PowerPoint PPT Presentation

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The New Standard / SigmaDDR-IIIe SigmaQuad-IIIe Quad Data Rate, - - PowerPoint PPT Presentation

High Transaction Rate Memories: The New Standard / SigmaDDR-IIIe SigmaQuad-IIIe Quad Data Rate, B2 at 675 MHz GS8673 1.35 GHz Transaction Rate 72Mbit ECCRAM 1.35 Gb/s per pin data 97 Gb/s per part bandwidth Quad


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SLIDE 1

High Transaction Rate Memories: The New Standard

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SLIDE 2

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SigmaQuad-IIIe

™ / SigmaDDR-IIIe ™

  • Quad Data Rate, B2 at 675 MHz
  • 1.35 GHz Transaction Rate
  • 1.35 Gb/s per pin data
  • 97 Gb/s per part bandwidth
  • Quad Data Rate, B4 at 675 MHz
  • 1.35 Gb/s per pin data
  • 97 Gb/s per part bandwidth
  • Double Data Rate, B2 at 675 MHz
  • 1.35 Gb/s per pin data
  • 48 Gb/s per part bandwidth
  • On-Chip ECC: virtually zero SER

260 ball, 1 mm pitch BGA

GS8673 72Mbit ECCRAM

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SLIDE 3

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Development Strategy Part 1: Keep What Works

  • BGA Package with 1 mm Pad Pitch
  • No special assembly requirements
  • Conventional Control Truth Table
  • Familiar Read and Write protocols
  • Echo Clocks and Output Valid Signals
  • DLL-controlled Output Data timing
  • Programmable Output Driver Impedance
  • ZQ control of Output impedance
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SLIDE 4

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Development Strategy Part 2: Fix What Doesn’t

  • Better Signal Integrity
  • Larger Output Data Valid Window
  • New High Performance Pinout
  • User-programmable ODT (On-Die Input Termination)
  • Programmable value
  • Selectable input pin coverage
  • KD & KD# Data Input Clocks
  • Lower Signaling and Core Power Consumption
  • 1.3 V VDD
  • 1.2 V JEDEC BIC thru 1.5 V JEDEC HSTL I/O
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SLIDE 5

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Higher Performance Pinouts

SigmaQuad/DDR: I, II, II+ SigmaQuad/DDR: IIIe

165 BGA : 11 x 15 Array, 15 x 17 mm, 1 mm pitch 260 BGA: 13 x 20 Array, 14 x 22 mm, 1 mm pitch

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SLIDE 6

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Improved Data Valid Windows

165 BGA @ 333 MHz

40ohm driver; 60ohm thevenin termination 666 MHz data rate; 1.5 V output voltage Result: ~780ps eye @ 1500ps Tcycle 52% data valid window

Modern 260 BGA @ 500 MHz

40ohm driver; 60ohm thevenin termination 1.0 GHz data rate; 1.2 V output voltage Result: ~760ps eye @ 1000ps Tcycle 76% data valid window

~780ps ~760ps

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SLIDE 7

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Type-IIIe SRAMs - Ordering Options

Product Option: Read Latency (cycles) Speed Bins (MHz) Quad Data Rate Burst of 2 2, 3 500 550 625 675 Quad Data Rate Burst of 4 2, 3 500 550 625 675 Double Data Rate Burst of 2 2, 3 500 550 625 675

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SLIDE 8

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Type-IIIe SRAMs are Qualified and Shipping in Volume

Questions? IIIeinfo@gsitechnology.com

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SLIDE 9

Thank You.