Chapter 7 Utilities for High-Level Descriptions Part 2 1 - - PowerPoint PPT Presentation

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Chapter 7 Utilities for High-Level Descriptions Part 2 1 - - PowerPoint PPT Presentation

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Chapter 7 Utilities for High-Level Descriptions Part 2 1 benyamin@mehr.sharif.edu Array Type Declaration TYPE arry_name IS ARRAY range OF element_type TYPE qit_nibble IS ARRAY (3 DOWNTO 0) OF qit; TYPE qit_byte IS ARRAY (1 TO 8) OF qit;

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Chapter 7

Utilities for High-Level Descriptions Part 2

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Array Type Declaration

TYPE arry_name IS ARRAY range OF element_type TYPE qit_nibble IS ARRAY (3 DOWNTO 0) OF qit; TYPE qit_byte IS ARRAY (1 TO 8) OF qit; TYPE qit_word IS ARRAY (1 TO 16) OF qit; TYPE byte IS ARRAY (7 DOWNTO 0) OF BIT;

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Array Type Declaration

TYPE qit_mem IS ARRAY ( 0 TO 7 ) OF qit_nibble;

TYPE mem IS ARRAY( 0 TO 3) OF byte;

TYPE mem2 IS ARRAY (3 DOWNTO 0,0 TO 7) OF BIT;

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Array Initialization

SIGNAL x: qit_byte := ( 5=>’Z’ , OTHERS=>’1’); SIGNAL x: qit_byte := ( 1 DOWNTO 0=>’Z’ ,3 TO 4=>’X’ , OTHERS=>’1’); SIGNAL x: qit_byte := (OTHERS=>’Z’);

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2-D Array Initialization

SIGNAL m:mem2:=( (‘0’,’1’,’1’,’1’,’1’,’0’,’1’,’Z’), (‘0’,’1’,’1’,’0’,’1’,’0’,’1’,’Z’), (‘Z’,’1’,’0’,’1’,’1’,’0’,’1’,’Z’), (‘1’,’1’,’1’,’0’,’1’,’0’,’1’,’Z’), ); SIGNAL m:mem2:=(OTHERS=>”01010101”); SIGNAL m:mem2:=(OTHERS=>(OTHERS=>’Z’));

SIGNAL m:mem2:=(OTHERS=>(0 TO 1 =>’1’,OTHERS=>’0’));

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Array Indexing

SIGNAL x8: qit_byte; SIGNAL x16: qit_word; SIGNAL mq:qit_mem; SIGNAL m:mem2;

… x8<=x16(11 downto 4); x16(15 downto 12) <=x8(4 downto 1); (x8(1),x8(3),x8(2))<=x16(10 downto 8); x8<=x16(1)& x16(3)& x16(2)& x16(15 downto 11); mq(1)<=x8; mq(3)(5)<=x16(3); X16(10 downto 8)<=mq(4)(3 DOWNTO 1); X8(1)<=to_qt ( m(2,5) );

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Noninteger Indexing

TYPE qit_2d IS ARRAY(qit,qit) OF qit; CONSTANT qit_nand2 :qit_2d :=(

  • - ‘0’ ‘1’ ‘Z’ ‘X’

(‘1’,’1’,’1’,’1’), –’0’ (‘1’,’0’,’0’,’X’), –’1’ (‘1’,’0’,’0’,’X’), –’Z’ (‘1’,’X’,’X’,’X’) –’X’ );

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Noninteger Indexing

USE WORK.basic_utilities.ALL; ENTITY nand2 IS PORT(i1,i2:IN qit;o1:OUT qit); END; ARCHITECTRE table_based OF nand2 IS BEGIN

  • 1<= qit_nand2(i1,i2) AFTER 10 NS;

END;

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Noninterger Indexing

CONSTANT qit_nand2:qit_2d :=( ‘0’ => (OTHERS=>’1’), ‘X’ => (‘0’ => ‘1’ , OTHERS=> ‘X’), OTHERS =>(‘0’ =>’1’ ,’X’ =>’X’,OTHERS=>’0’) );

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Unconstrained Arrays

TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT; TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF BIT;

TYPE INTEGER_VECTOR IS ARRAY (NATURAL RANGE <>) OF INTEGER; Type mark

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File Type

  • VHDL standard package provides file i/o
  • perations
  • Default file type is text file
  • Users can define their own file types
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File Type Declaration

TYPE logic_data IS FILE OF CHARACTERS;

TYPE std_file Is FILE OF std_logic_vector(7 downto 0);

TYPE type_name IS FILE OF element_type

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FILE Declaration

FILE file_name : file_type [OPEN mode] [IS physical_file_name]; Kind ::= READ_MODE | WRITE_MODE|APPEND_MODE;

FILE inp1 : logic_data; FILE inp2 : logic_data IS “input.dat”; FILE inp3 : logic_data OPEN READ_MODE IS “input.dat”;

Open file in READ_MODE

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File Operations – Open/Close

FILE_OPEN(file_var,physical_file_name,mode) FILE_CLOSE(file_var);

FILE_OPEN(inp1,”input.dat”,WRITE_MODE); FILE_OPEN(inp2,”input.dat”,READ_MODE); FILE_OPEN(inp3,”input.dat”); … FILE_CLOSE(inp1); FILE_CLOSE(inp2);

READ_MODE is default

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FILE Operations – End of File

ENDFILE(file_var)

  • Returns TRUE if subsequent operation

can not be done from the file

WHILE NOT ENDFILE(f1) LOOP

  • -Some FILE operations on f1

END LOOP;

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FILE I/O

READ(file_var,variable); WRITE(file_var,variable);

  • Type of variable must be same as file type
  • All file operations are sequential

WRITE(f1,”01010100”); Signal a:std_logic_vector(7 downto 0); READ(f1,a);

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FILE I/O Example

PROCEDURE assign_bits( SIGNAL s:OUT BIT; file_name: IN STRING; period : IN TIME) IS VARIABLE char :CHARACTER; VARIABLE current: TIME:=0 NS; FILE iput_value_file : logic_data; BEGIN FILE_OPEN(input_value_file,file_name,READ_MODE); WHILE NOT ENDFILE(input_value_file) LOOP READ(input_value_file,char); IF char=‘0’ OR char=‘1’ THEN current:=current+period; IF char=‘0’ THEN s<=TRANSPORT ‘0’ AFTER current; ELSIF char=‘1’ THEN s<=TRANSPORT ‘1’ AFTER current; END IF; END IF; END LOOP; END;

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Operator Overloading

  • Operators can be represented by their

strings c<=a AND b; c<=“AND” (a,b);

  • Each subprogram with different types of

parameters can be distinguished from each other

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NAND Overloading

FUNCTION “NAND” (a,b:qit) RETURN qit IS CONSTANT qit_nand2 :qit_2d :=(

  • - ‘0’ ‘1’ ‘Z’ ‘X’

(‘1’,’1’,’1’,’1’), –’0’ (‘1’,’0’,’0’,’X’), –’1’ (‘1’,’0’,’0’,’X’), –’Z’ (‘1’,’X’,’X’,’X’) –’X’ ); BEGIN return qit_nand2(a,b); END;

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Not Overloading

TYPE qit_1d IS ARRAY(qit) OF qit; … FUNCTION “NOT” (a:qit) RETURN qit IS CONSTANT qit_not :qit_1d :=(‘1’,’0’,’0’,’X’); BEGIN return qit_not(a); END;

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RC Calculation

PACKAGE basic_utilities IS TYPE capacitance … TYPE resistance … FUNCTION “*” (a:resistance;b:capacitance) RETURN TIME; END; PACKAGE BODY basic_utilities IS FUNCTION “*” (a:resistance;b:capacitance) RETURN TIME IS BEGIN RETURN (( a/ 1 l_o) * ( b / 1 ffr) * 1 FS) / 1000; END; END;

CONSTANT c:capacitance:= 5 ffr; CONSTANT r:resistance:=10 ohm;

  • 1<= i1 and i2 AFTER r*c;
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Case Statement

  • Multiple if –elsif statements cam be replaced by

Case statement

  • Var can be from each type with defined “=“
  • perator

CASE var IS WHEN equality1 => statements WHEN equality2 => statements WHEN equalityn => statements WHEN OTHERS => statements END CASE;

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Assign_bits Using CASE

PROCEDURE assign_bits( SIGNAL s:OUT qit; file_name: IN STRING; period : IN TIME) IS VARIABLE char :CHARACTER; VARIABLE current: TIME:=0 NS; FILE iput_value_file : logic_data; BEGIN FILE_OPEN(input_value_file,file_name,READ_MODE); WHILE NOT ENDFILE(input_value_file) LOOP READ(input_value_file,char); current:=current+period; CASE char IS WHEN ‘0’ => s<=TRANSPORT ‘0’ AFTER current; WHEN ‘1’ =>s<=TRANSPORT ‘1’ AFTER current; WHEN ‘Z’ =>s<=TRANSPORT ‘Z’ AFTER current; WHEN ‘X’ =>s<=TRANSPORT ‘X’ AFTER current; WHEN OTHERS => current:=current-period; END CASE; END LOOP; END;

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Subtypes

  • Subtypes consists the subsets of the

values of the previously defined type

  • The original type is called BASE-TYPE
  • All types are subtypes of themselves
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Subtype Declaration

SUBTYPE subtype_name IS base_type range

SUBTYPE compatible_nibble_bits IS BIT_VECTOR(3 DOWNTO 0); SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9; SUBTYPE rit IS qit RANGE ‘0’ TO ‘Z’; SUBTYPE bin IS qit RANGE ‘0’ TO ‘1’;

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Std_logic Subtypes

Subtype UX01Z IS std_logic RANGE ‘U’ TO ‘Z’

UX01Z

Subtype UX01 IS std_logic RANGE ‘U’ TO ‘1’

UX01

Subtype X01Z IS std_logic RANGE ‘X’ TO ‘Z’

X01Z

Subtype X01 IS std_logic RANGE ‘X’ TO ‘1’

X01 Values Subtype

Signal a : X01Z :=‘Z’; Signal b : UX01Z :=‘U’;

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Record Types

  • Array is a composit type with the same

element types

  • Records are composite type with different

element types

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Record Type Declaration

TYPE rec_type IS RECORD element_name : type; {element_name : type;} END RECORD;

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Record Type Declaration

TYPE opcode IS (sta,lda,add,sub,and,jmp,nop); TYPE mode IS RANGE 0 TO 3;

TYPE address IS BIT_VECTOR(10 DOWNTO 0); TYPE instruction IS RECORD

  • pc:opcode;

mde:mode; adr:address; END RECORD;

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Record Type Declaration

SIGNAL instr: instruction :=(nop,0,”00000000000”);

Instr.opc<=sta; Instr.mde<=2; Instr.adr<=“00011110011”;

Instr<=(adr=>(OTHERS=>’1’) , mde=>2 , opc=>sub);

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Alias Declaration

ALIAS new_name : type IS object;

  • An object, an indexed part of it, or a slice
  • f it can be given alternative names
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Alias Declaration

Signal flag:BIT_VECTOR(7 DOWNTO 0); SIGNAL instr: instruction :=(nop,0,”00000000000”); ALIAS carry : BIT IS flag(7);

ALIAS nibble_flag: BIT_VECTOR(4 DOWNTO 1) IS flag(3 DOWNTO 0);

ALIAS opcode1:BIT_VECTOR(10 DOWNTO 0) IS Instr.opc;

ALIAS page: BIT_VECTOR(2 DOWNTO 0) IS instr.adr(10 DOWNTO 8); ALIAS offset: BIT_VECTOR(7 DOWNTO 0) IS instr.adr(7 DOWNTO 0); page<=“001”;

  • ffset<=X“F1”;

Hexadecimal String

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Access Type

  • Incomplete type declaration

TYPE node;

  • Access Type Declaration

TYPE pointer IS ACCESS node;

  • Complete type declaration

TYPE node IS RECORD

data : INTEGER; next : pointer;

END RECORD;

node node node node

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Access Type Usage

VARIABLE head,t1 : pointer :=NULL; head := NEW node; -get memory head.next= NEW node; head.data=1; t1=head; DEALLOCATE(t1); -release memory

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Shared Variable

SHARED VARIABLE id_list: type [:= initial];

  • A shared variable declared in PACKAGE is accessible to all

VHDL bodies that use package

  • A shared variable declared in Architecture declarative part

is only accessible to architecture body

  • Share variables are not protected against multiple

simultaneous READ/WRITE operations

  • Signal Semaphores for creating such a protection can be

done in VHDL

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Shared Variable Example

SHARED VARIABLE sink:INTEGER:=0;

SHARED VARIABLE a:BIT_VECTOR(1 to 5);

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Type Conversions

  • Type of expressions are not known from

the context in which they are used in two methods are offered:

– Type conversion

  • new_compatible_type(expression)

std_a<=std_logic(bit_data);

– Type qualification

  • new_compatible_type’ expression

std_vec_a<=std_logic_vector’(”000111”);

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Predefined Attributes

  • VHDL provide functions for more efficient coding
  • r mechanism for modeling hardware

characteristics

  • Attributes can be applied to arrays, types,

signals and entities

  • bject’attribute

a’RANGE Clk’EVENT

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Array Attributes

a’LOW(2) Lower Bound ‘LOW 3 a’LEFT(1) Left Bound ‘LEFT 7 a’HIGH(2) Upper Bound ‘HIGH 7 DOWNTO 0 0 TO 3 a’REVERSE_RANGE(2) a’ REVERSE_RANGE Reverse Range ‘REVERSE_RANGE TRUE FALSE a’ASCENDING(2) a’ASCENDING(1) TRUE If Ascending ‘ASCENDING 7 a’RIGHT a’RIGHT(2) Right Bound ‘RIGHT 4 a’LENGTH Length ‘LENGTH 0 TO 7 3 DOWNTO 0 a’RANGE(2) a’RANGE(1) Range ‘RANGE Result Example Description Attribute

TYPE mem2 IS ARRAY ( 3 DOWNTO 0 , 0 TO 7 ) OF BIT; SIGNAL a: mem2;

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Type Attributes

1 ‘0’ POSITIVE’LOW rit’LOW Lower Bound

  • f type

‘LOW qit rit’BASE Base of type ‘BASE Large ‘Z’ INTEGER’HIGH rit’HIGH Upper Bound

  • f type

‘HIGH ‘Z’ ‘X’ rit’RIGHT qit’RIGHT Right Bound

  • f type

‘RIGHT ‘0’ ‘0’ rit’LEFT qit’LEFT Left bound of type ‘LEFT Result Example Description Attribute

TYPE qit IS (‘0’,’1’,’Z’,’X’); SUBTYPE rit IS qit RANGE ‘0’ TO ‘Z’;

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Type Attributes

TRUE qit’ASCENDING TRUE If range is ascending ‘ASCENDING ‘0’ Rit’PRED(‘1’) Value, before value V in base of type ‘PRED(V) ‘Z’ ‘X’ rit’RIGHTOF(‘1’) rit’RIGHTOF(‘Z’) Value, right of value V in base of type ‘RIGHTOF(V) ‘0’ ERROR rit’LEFTOF(‘1’) rit’LEFTOF(‘0’) Value, left of value V in base of type ‘LEFTOF(V) “’Z’” qit’IMAGE(‘Z’) Converts value V of type to string ‘IMAGE(V) Result Example Description Attribute

TYPE qit IS (‘0’,’1’,’Z’,’X’); SUBTYPE rit IS qit RANGE ‘0’ TO ‘Z’;

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Type Attributes

‘1’ rit’VALUE(“’1’”) Converts string S to value of type ‘VALUE(S) 2 qit’POS(‘Z’) Position of value V in base

  • f type

‘POS(V) ‘X’ qit’SUCC(‘Z’) Value, after value V in base

  • f type

‘SUCC(V) ‘X’ qit’VAL(3) Value at position P in base of type ‘VAL(P) Result Example Description Attribute

TYPE qit IS (‘0’,’1’,’Z’,’X’); SUBTYPE rit IS qit RANGE ‘0’ TO ‘Z’;

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Signal Attributes

BOOLEAN a’STABLE a’STABLE( 5 NS) TRUE if signal has not changed in the last specified time ‘STABLE SIGNAL a’DELAYED a’DELAYED(3 ns) A copy of signal, but delayed ‘DELAYED BOOLEAN a’EVENT If signal changes in current time ‘EVENT Result Example Description Attribute

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Edge Detection

q<=d WHEN clk=‘0’ AND NOT Clk’STABLE; IF( clk=‘0’ AND Clk’EVENT) THEN … q<=d WHEN clk=‘1’ AND NOT Clk’STABLE; IF( clk=‘1’ AND Clk’EVENT) THEN …

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Signal Attribute Example

ENTITY tff IS PORT(d,clk:IN std_logic;q:OUT std_logic); END; ARCHITECTURE setup OF tff IS signal tmp:std_logic :=‘0’; BEGIN

tmp<= NOT tmp WHEN (clk=‘0’ AND clk’EVENT) AND (d’STABLE( 10 NS)) ELSE tmp;

q<=tmp AFTER 8 Ns;

END;

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Entity Attributes

“tff” tff’SIMPLE_NA ME Entity Name in string ‘SIMPLE_NAME “:alu(gate_level):tfflable @tff(setup)” tff’INSTANCE_N AME An string containing entit, architecture and lables ‘INSTANCE_NAME “:alu:tfflable” tff’PATH_NAME An string containing entity names and instantiation lables ‘PATH_NAME Result Example Description Attribute

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User Defined Attributes

Attribute Declaration in Package or Entity ATTRIBUTE att_name : type;

  • Attribute Usage in Entity or Architecture

ATTRIBUTE att_name OF object_name : object_type IS value;

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User Defined Attributes

PACKAGE att IS TYPE timing IS RECORD rise,fall:TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING END; USE WORK.att.ALL; ENTITY dff IS PORT(d,clk:IN BIT;q:OUT BIT); ATTRIBUTE sub_dir OF dff : ENTITY IS “d:\design\vhdl”; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 8 NS); END; ARCHITECTURE attrib OF dff IS SIGNAL tmp:BIT:=‘0’; BEGIN tmp<= d WHEN (clk=‘0’ AND clk’EVENT); q<=‘1’ AFTER q’delay.rise WHEN tmp=‘1’ ELSE ‘0’ AFTER q’delay.fall; END;