FPGA Reconfiguration Politecnico di Milano Seminar Room, Bld 20 4 - - PowerPoint PPT Presentation

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FPGA Reconfiguration Politecnico di Milano Seminar Room, Bld 20 4 - - PowerPoint PPT Presentation

Nov 01, 2023 655 likes •1.26k views

Advanced Topics on Heterogeneous System Architectures FPGA Reconfiguration Politecnico di Milano Seminar Room, Bld 20 4 December, 2017 Antonio R. Antonio R. Miele Miele Marco D. Santambrogio Marco D. Santambrogio

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SLIDE 1

Advanced Topics on Heterogeneous System Architectures

Politecnico di Milano Seminar Room, Bld 20 4 December, 2017 Antonio R. Antonio R. Miele Miele Marco D. Santambrogio Marco D. Santambrogio Politecnico di Milano

FPGA Reconfiguration

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SLIDE 2

Reconfiguration in everyday life

2

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SLIDE 3

Reconfiguration in everyday life

Soccer

(Par%al – Sta%c)

3

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SLIDE 4

Reconfiguration in everyday life

Soccer

Football

(Complete – Sta%c) (Par%al – Sta%c)

4

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SLIDE 5

Reconfiguration in everyday life

Soccer

Football

(Complete – Sta%c)

Hockey

( P a r % a l – D y n a m i c ) (Par%al – Sta%c)

5

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SLIDE 6

SoC Reconfiguration

6

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SLIDE 7

SoC Reconfiguration

7

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SLIDE 8

SoC Reconfiguration

8

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SLIDE 9

SoC Reconfiguration

9

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SLIDE 10

SoC Reconfiguration

10

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SLIDE 11

SoC Reconfiguration

11

"MANAGER"

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SLIDE 12

SoC Reconfiguration

12

"MANAGER"

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SLIDE 13

SoC Reconfiguration

13

"MANAGER"

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SLIDE 14

SoC Reconfiguration

14

"MANAGER"

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SLIDE 15

" M A N A G E R "

SoC Reconfiguration

15

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SLIDE 16

" M A N A G E R "

SoC Reconfiguration

16

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SLIDE 17

" M A N A G E R "

SoC Reconfiguration

17

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SLIDE 18

SoC Reconfiguration

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"MANAGER"

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SLIDE 19

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

19

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SLIDE 20

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

20

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 21

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

21

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

WHO

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SLIDE 22

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

22

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

WHO

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SLIDE 23

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

23

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 24

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

24

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM GA

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SLIDE 25

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

25

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 26

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

26

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 27

SoMC Reconfiguration Scenario

  • Embedded VS External
  • Complete VS Partial
  • Dynamic VS Static

27

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 28

SoMC Reconfiguration Scenario

28

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM

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SLIDE 29

FPGA FPGA FPGA

BOARD/FPGAs CARD

HOST

(e.g., PC)

SYSTEM GA

SoMC Reconfiguration Scenario

29

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SLIDE 30

30

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SLIDE 31

Some Definitions

  • Object Code

Object Code: the executable active physical (either HW or SW) implementation of a given functionality

  • Core

Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)

31

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SLIDE 32

Some Definitions

  • Object Code

Object Code: the executable active physical (either HW or SW) implementation of a given functionality

  • Core

Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)

32

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SLIDE 33

Some Definitions

  • Object Code

Object Code: the executable active physical (either HW or SW) implementation of a given functionality

  • Core

Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)

  • IP-Core

IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)

  • 33
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SLIDE 34

Some Definitions

  • Object Code

Object Code: the executable active physical (either HW or SW) implementation of a given functionality

  • Core

Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)

  • IP-Core

IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)

  • Reconfigurable Functional Unit

Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture

34

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SLIDE 35

Some Definitions

  • Object Code

Object Code: the executable active physical (either HW or SW) implementation of a given functionality

  • Core

Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)

  • IP-Core

IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface)

  • Reconfigurable Functional Unit

Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture

  • Reconfigurable Region

Reconfigurable Region: a portion of the device area used to implement a reconfigurable core

35

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SLIDE 36

36

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SLIDE 37

5 W

  • who

who controls the reconfiguration

37

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SLIDE 38

5 W

  • who

who controls the reconfiguration

  • where

where the reconfiguration cotroller is located

38

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SLIDE 39

5 W

  • who

who controls the reconfiguration

  • where

where the reconfiguration cotroller is located

  • when

when the configurations are generated

39

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SLIDE 40

5 W

  • who

who controls the reconfiguration

  • where

where the reconfiguration cotroller is located

  • when

when the configurations are generated

  • which

which is the granularity of the reconfiguration

40

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SLIDE 41

5 W

  • who

who controls the reconfiguration

  • where

where the reconfiguration cotroller is located

  • when

when the configurations are generated

  • which

which is the granularity of the reconfiguration

  • in what

what dimension the reconfiguration operates

41

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SLIDE 42

5 W

  • who

who controls the reconfiguration

  • where

where the reconfiguration cotroller is located

  • when

when the configurations are generated

  • which

which is the granularity of the reconfiguration

  • in what

what dimension the reconfiguration operates

42

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SLIDE 43

Physical Coordinates

43

4-Slice VIIP CLB

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SLIDE 44

Physical Coordinates

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4-Slice VIIP CLB

SLICE

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SLIDE 45

Physical Coordinates

Y X

45

4-Slice VIIP CLB

SLICE

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SLIDE 46

Physical Coordinates

Y X

67 66

46

4-Slice VIIP CLB

SLICE

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SLIDE 47

Physical Coordinates

Y X

67 66 75 74

47

4-Slice VIIP CLB

SLICE_X67Y75

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SLIDE 48

Physical Coordinates

SLICE_X67Y75

Y X

67 66 75 74 SLICE_X66Y74

48

4-Slice VIIP CLB

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SLIDE 49

Physical Coordinates

Switch Box SLICE

Y X

67 66 75 74 SLICE_X66Y74

49

4-Slice VIIP CLB

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SLIDE 50

Reconfigurable Region Definition

50

The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file

50

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SLIDE 51

Reconfigurable Region Definition

51

The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file

AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127;

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SLIDE 52

Reconfigurable Region Definition

52

The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file

AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP "RR1" RANGE = RAMB16_X2Y9:RAMB16_X2Y15;

52

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SLIDE 53

RR Area Constraints

53

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SLIDE 54

RR Area Constraints

54

Xilinx VIIP Xilinx S3

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SLIDE 55

RR Area Constraints

55

Xilinx VIIP Xilinx S3

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SLIDE 56

RR Area Constraints

Xilinx VIIP Xilinx S3

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SLIDE 57

RR Area Constraints

Xilinx VIIP Xilinx S3 Xilinx V4

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SLIDE 58

Advanced Topics on Heterogeneous System Architectures

Politecnico di Milano Seminari Room, Bld 20 4 December, 2017 Antonio R. Antonio R. Miele Miele Marco D. Santambrogio Marco D. Santambrogio Politecnico di Milano

FPGA Reconfiguration Questions…