Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs - - PowerPoint PPT Presentation

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Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs - - PowerPoint PPT Presentation

Sep 17, 2023 38 likes •91 views

Intro Prop Res Summary Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs Petter K allstr om and Oscar Gustafsson Link oping University Department of Computer Engineering 1 Intro Prop Res Summary Introduction

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SLIDE 1

Intro Prop Res Summary

Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs

Petter K¨ allstr¨

  • m and Oscar Gustafsson

Link¨

  • ping University

Department of Computer Engineering

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SLIDE 2

Intro Prop Res Summary

Introduction The Virtex 6 basic cell. The normal adder. Large N gives long critical path. Each LUT6 controls the propagate and generate signal.

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Intro Prop Res Summary

Proposed Adder The proposed approach. Decompose N into K LSBs and M MSBs. (cc) – K/2 carry compr. cells (so) – K/2 sum out cells (fa) – M normal full adder cells In total 2K/2 + M = N LUTs, i.e. no more than a normal adder. Optimum M = 36.

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Intro Prop Res Summary

Result Normal vs Proposed

32 64 96 128 160 192 224 256 1 2 3 4 5 Word length N [bits] Critical path [ns] M = 0 M = 36 M = 56 Normal adder (M = N ) ⋆ ⋆ ⋆

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SLIDE 5

Intro Prop Res Summary

Summary The proposed adder architecture Twice the carry speed in parts of the adder without pipelining Same LUT count as a normal adder Efficient for long word lengths Thank you!

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