Adders Lecture 12 CS301 Administrative Read Appendix C.5, - PowerPoint PPT Presentation

Adders Lecture 12 CS301

Administrative • Read Appendix C.5, C.7-C.10 • Program #1 due 10/24

FP Bias • Infinity is represented as w exponent is all 1s w significand is all 0s

Review • MUX • DeMux • Decoder • Encoder

Combinational Logic • Half-Adder w No carry in Carry A B Sum Out 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 A ⊕ B AB

1-bit Full Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in

Combinational Logic • Full Adder Note: C out = (b C in ) + (a C in ) + (a b) + (a b C in ) = (b C in ) + (a C in ) + (a b) = (a b) + (a + b) C in

Ripple Carry Adder • Construct n-bit adder with n 1-bit adders • Delay is problem • Faster alternative: w Carry-lookahead adder

Designing connections • Problem: Ripple-carry adder is too slow w Each carry must wait for all previous units to complete execution • Solution:

Designing connections • Problem: Ripple-carry adder is too slow w Each carry must wait for all previous units to complete execution • Solution: w Quickly get information for carries w Compute carries in parallel

1b Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in w C out = AB + AC in + BC in

Carry Look-ahead We already know: c i+1 = (b i  c i ) + (a i  c i ) + (a i  b i ) = (a i  b i ) + c i  (a i + b i )

Carry Look-ahead We already know: c i+1 = (b i  c i ) + (a i  c i ) + (a i  b i ) = (a i  b i ) + c i  (a i + b i ) Generate Propagate = Gi + Ci  Pi Let’s calculate c i+1 without waiting for c i

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Lookahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C2 P0 G0 C1 P3 G3 P2 G2 P1 G1 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2

Carry Look-ahead B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] 1-bit ALU 1-bit ALU 1-bit ALU 1-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2

Why is it Faster?

Why is it Faster? 4 th bit waits only for p&g to be calculated, not all of the • computations from bits 0-2 Only three levels of computation • C1 = G0 + C0 * P0 C2 = G1 + C1 * P1 = G1 + ( G0 + C0 * P0 ) * P1 = G1 + G0 * P1 + C0 * P0 * P1 C3 = G2 + C2 * P2 = G2 + (G1 + G0 * P1 + C0 * P0 * P1) * P2 = G2 + G1 * P2 + G0 * P1 * P2 + C0 * P0 * P1 * P2 w Gi and Pi w AND w OR

The Next Step A[12-15] A[8-11] A[4-7] A[0-3] B[0-3] B[12-15] B[8-11] B[4-7] 4-bit ALU 4-bit ALU 4-bit ALU 4-bit ALU C3 C2 C1 P3 G3 P2 G2 P1 G1 P0 G0 C0 Carry Look-ahead Logic Now what is the equation for Pi & Gi? They are for the 4-bit ALU, not just one bit!

Basic Memory Cells and Sequential Logic

Sequential Logic and Clocks • Sequential logic retains state • Clocks specify when that state should be updated • System using clocks called synchronous

Clock Falling • Signal with fixed edge cycle time ( T cycle) Rising edge • Frequency: 1/ T cycle • T cycle has two parts delineated by two edges T cycle w Clock high w Clock low

Clocks (cont.)

Memory Elements • All memory elements store state w Output depends both on inputs and the value stored inside the memory element • Thus: All logic blocks containing memory elements contain state and are sequential!

Unclocked Latch

Clocked Latch

D Flip-Flop • D flip flop stores 1 bit of data • Created from 2 edge triggered D latches • Only takes in new inputs when clock is high

Register D flip-flop allows us to store 1 bit • Programmers don’t programming in bits, but • w char = 8 b w integer = 32 b w ... String n D flip-flops together to store n bits • b3 b2 b1 b0 4b register implement with D flip-flops

Register Files • Contains set of registers accessed by register num w Input: register number w Output: data in register n entry register file

Register Files • Components w Array of registers built from flip-flops • Port w Access point w Read port § register num w Write port § register num, clock, data 2 read ports / 1 write port

Register File:   Read Ports

Register File:   Write Port

Comparator • Comparator has three output lines w A<B w A=B w A>B

Comparator

We Almost Have All the Pieces • Inverter, AND, OR • Multiplexor and demultiplexor • Decode and encoder • Comparator • Ripple carry adder and carry lookahead adder w Half and full adder • Register file w Registers w D flip flop

Arithmetic Logic Unit • Circuitry that does arithmetic (+/-) and logical operations (AND/OR) • MIPS has 32b quantities so ALU needs to handle 32b numbers • Combine 32 1-b ALUs to create 32b ALU

AND/OR

1b Adder • Three inputs: w A w B w C in • Two outputs: w Sum = (A ⊕ B) ⊕ C in w C out = AB + (A ⊕ B) C in

1b ALU

32b ALU

Adders Lecture 12 CS301 Administrative Read Appendix C.5, - PowerPoint PPT Presentation

Adders Lecture 12 CS301 Administrative Read Appendix C.5, C.7-C.10 Program #1 due 10/24 FP Bias Infinity is represented as w exponent is all 1s w significand is all 0s Review MUX DeMux Decoder Encoder

Outline Digital CMOS design Arithmetic operators Adders Adders Comparators Shifters

Unit 12 Adders & Arithmetic Circuits 12.2 Learning Outcomes I understand what gates are

Unit 11 Adders & Arithmetic Circuits 11.2 Learning Outcomes I understand what gates are

Combinational Circuits Chapter 3 S. Dandamudi Outline Introduction Adders

Combinational Circuits Chapter 3 S. Dandamudi Outline Introduction Adders

Optimal Sparseness in Binary Adders ARITH 22 Lyon, France 2015 Outline Parallel Adders

Adding Adders in County Durham Agenda Background Vulnerability of adders Connecting

EE 457 Unit 2b Fast Adders (Carry-Lookahead Adder) 2 Carry-Lookahead Adders FAST ADDERS 3

EE 457 Unit 2b Fast Adders Carry-Lookahead Adders (Carry-Lookahead Adder) FAST ADDERS 2b.3

Learning Outcomes I understand what gates are used to design half and full adders Unit 12

Conditional Sum Adders 8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 4-7 =

Where are we? Subsystem Design Registers and Register Files Adders and ALUs Simple

Where are we? Data Path Design Subsystem Design Registers and Register Files Adders

ECE 3060 VLSI and Advanced Digital Design Lecture 13 Datapath1: ALUs and Adders Datapath

Lecture 12: Adders, Sequential Circuits Todays topics: Carry-lookahead adder

Lesson 7 Combinational Logic Circuits Concepts Introduced Adders Multiplexers

Systems Ripple Carry Adder Shankar Balachandran* Associate Professor, CSE Department Indian

Outline Introduction to CMOS VLSI Single-bit Addition Design Carry-Ripple Adder

Numbers and Arithmetic Prof. Hakim Weatherspoon CS 3410 Computer Science Cornell University

Lesson 6 Combinational Logic Circuits Gate Review AND Gate OR Gate NOT Gate NAND

Digital Logic and Transistors The invention of the transistor made binary logic the cheapest and

lecture 4 Combinational logic 2 - ROM - arithmetic circuits - arithmetic logic unit (ALU)

Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs Petter K allstr om and

New Struc w Structure ture for A for Adde dder with r with r Im Improve proved Spe d

Adders Lecture 12 CS301 Administrative Read Appendix C.5, - PowerPoint PPT Presentation

Adders Lecture 12 CS301 Administrative Read Appendix C.5, C.7-C.10 Program #1 due 10/24 FP Bias Infinity is represented as w exponent is all 1s w significand is all 0s Review MUX DeMux Decoder Encoder

Outline Digital CMOS design Arithmetic operators Adders Adders Comparators Shifters

Unit 12 Adders &amp; Arithmetic Circuits 12.2 Learning Outcomes I understand what gates are

Unit 11 Adders &amp; Arithmetic Circuits 11.2 Learning Outcomes I understand what gates are

Combinational Circuits Chapter 3 S. Dandamudi Outline Introduction Adders

Combinational Circuits Chapter 3 S. Dandamudi Outline Introduction Adders

Optimal Sparseness in Binary Adders ARITH 22 Lyon, France 2015 Outline Parallel Adders

Adding Adders in County Durham Agenda Background Vulnerability of adders Connecting

EE 457 Unit 2b Fast Adders (Carry-Lookahead Adder) 2 Carry-Lookahead Adders FAST ADDERS 3

EE 457 Unit 2b Fast Adders Carry-Lookahead Adders (Carry-Lookahead Adder) FAST ADDERS 2b.3

Learning Outcomes I understand what gates are used to design half and full adders Unit 12

Conditional Sum Adders 8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 4-7 =

Where are we? Subsystem Design Registers and Register Files Adders and ALUs Simple

Where are we? Data Path Design Subsystem Design Registers and Register Files Adders

ECE 3060 VLSI and Advanced Digital Design Lecture 13 Datapath1: ALUs and Adders Datapath

Lecture 12: Adders, Sequential Circuits Todays topics: Carry-lookahead adder

Lesson 7 Combinational Logic Circuits Concepts Introduced Adders Multiplexers

Systems Ripple Carry Adder Shankar Balachandran* Associate Professor, CSE Department Indian

Outline Introduction to CMOS VLSI Single-bit Addition Design Carry-Ripple Adder

Numbers and Arithmetic Prof. Hakim Weatherspoon CS 3410 Computer Science Cornell University

Lesson 6 Combinational Logic Circuits Gate Review AND Gate OR Gate NOT Gate NAND

Digital Logic and Transistors The invention of the transistor made binary logic the cheapest and

lecture 4 Combinational logic 2 - ROM - arithmetic circuits - arithmetic logic unit (ALU)

Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs Petter K allstr om and

New Struc w Structure ture for A for Adde dder with r with r Im Improve proved Spe d

Unit 12 Adders & Arithmetic Circuits 12.2 Learning Outcomes I understand what gates are

Unit 11 Adders & Arithmetic Circuits 11.2 Learning Outcomes I understand what gates are