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CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16 Prof. Steven M. Nowick nowick@cs.columbia.edu Department of Computer Science (and Elect. Eng.) Columbia University New York, NY, USA Conditional Sum Adders 8-Bit

  1. CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16 Prof. Steven M. Nowick nowick@cs.columbia.edu Department of Computer Science (and Elect. Eng.) Columbia University New York, NY, USA

  2. Conditional Sum Adders

  3. 8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 4-7 = typical case (i.e. not near right side) y7 x7 y6 x6 y5 x5 y4 x4 c8 0 c7 0 c6 0 c5 0 0 0 0 0 FA FA FA FA s7 0 s6 0 s5 0 s4 0 y7 y6 x7 x6 y5 x5 y4 x4 c8 1 c7 1 c6 1 c5 1 1 1 1 1 FA FA FA FA s7 1 s6 1 s5 1 s4 1 #3

  4. 8-Bit Conditional Sum Adder: Level 2 Deriving Design for Bits 4-7 = typical case (i.e. not near right side) Notation: shows two 2-to-1 MUXes with the same select signal (c5 1 ) c6 0 c6 1 s5 0 s5 1 c5 1 c6 1-new S5 1-new #4

  5. 8-Bit Conditional Sum Adder: Levels 1 & 2 Deriving Design for Bits 4-7 = typical case (i.e. not near right side) y7 x7 y6 x6 y5 x5 y4 x4 c8 0 c7 0 c6 0 c5 0 0 0 0 0 FA FA FA FA s7 0 s6 0 s5 0 s4 0 y7 x7 y6 y5 x6 x5 y4 x4 c8 1 c7 1 c6 1 c5 1 1 1 1 1 FA FA FA FA s7 1 s6 1 s5 1 s4 1 c6 0 c8 0 c8 1 c6 1 s7 0 s5 0 s5 1 s7 1 c8 0 c6 0 c8 1 s7 0 c6 1 s5 0 s7 1 s5 1 c7 0 c5 0 c7 1 c5 1 c6 0-new S5 0-new c8 0-new S7 0-new c8 1-new S7 1-new c6 1-new S5 1-new #5

  6. 8-Bit Conditional Sum Adder: Levels 1 to 4 Deriving Design for Bits 4-7 = typical case (i.e. not near right side) Levels 1 through 4 (complete): see Conditional Sum Adder handout #6

  7. 8-Bit Conditional Sum Adder: Level 1 Deriving Design for Bits 0-3 = special case (i.e. at right side) y3 x3 y2 x2 y1 x1 y0 x0 c4 0 c3 0 c2 0 0 0 0 CIN C1 FA FA FA FA s3 0 s2 0 s1 0 s0 y3 y2 x3 x2 y1 x1 c4 1 c3 1 c2 1 1 1 1 FA FA FA s3 1 s2 1 s1 1 Note: no speculation of two options in bit 0, since CIN is known. #7

  8. 8-Bit Conditional Sum Adder: Level 1 & 2 Deriving Design for Bits 0-3 = special case (i.e. at right side) y3 x3 y2 x2 y1 x1 y0 x0 c4 0 c3 0 c2 0 0 0 0 CIN C1 FA FA FA FA s3 0 s2 0 s1 0 s0 y3 y2 x3 x2 y1 x1 c4 1 c3 1 c2 1 1 1 1 FA FA FA s3 1 s2 1 s1 1 c2 0 c4 0 c4 1 c2 1 s3 0 s1 0 s1 1 s3 1 c4 0 c4 1 s3 0 s3 1 c3 0 C1 c3 1 c2 0-new S1 0-new c4 0-new S3 0-new c4 1-new S3 1-new #8

  9. 8-Bit Conditional Sum Adder: Levels 1 to 3 Deriving Design for Bits 0-3 = special case (i.e. at right side) Levels 1 through 3 (complete): see Conditional Sum Adder handout #9

  10. 8-Bit Conditional Sum Adder: Final Design …see Conditional Sum Adder Handout for complete detailed design #10

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