CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2)
10/6/16
- Prof. Steven M. Nowick
Conditional Sum Adders 8-Bit Conditional Sum Adder: Level 1 - - PowerPoint PPT Presentation
CSEE 4823 Advanced Logic Design Handout: Lecture #10 (part 2) 10/6/16 Prof. Steven M. Nowick nowick@cs.columbia.edu Department of Computer Science (and Elect. Eng.) Columbia University New York, NY, USA Conditional Sum Adders 8-Bit
#3
FA y4 x4 s40 c50 FA y4 x4 s41 1 c51 FA y5 x5 s50 c60 FA y5 x5 s51 1 c61 FA y6 x6 s60 c70 FA y6 x6 s61 1 c71 FA y7 x7 s70 c80 FA y7 x7 s71 1 c81
#4
s50 s51 S51-new c60 c61 c61-new
c51
Notation: shows two 2-to-1 MUXes with the same select signal (c51)
#5
FA y4 x4 s40 c50 FA y4 x4 s41 1 c51
FA y5 x5 s50 c60 FA y5 x5 s51 1 c61 FA y6 x6 s60 c70 FA y6 x6 s61 1 c71 FA y7 x7 s70 c80 FA y7 x7 s71 1 c81 s50 s51 S51-new c60 c61 c61-new
c51
s70 s71 S70-new c80 c81 c80-new
c70
s70 s71 S71-new c80 c81 c81-new
c71
s50 s51 S50-new c60 c61 c60-new
c50
#6
Levels 1 through 4 (complete): see Conditional Sum Adder handout
#7
FA y0 x0 s0 CIN C1 FA y1 x1 s10 c20 FA y1 x1 s11 1 c21 FA y2 x2 s20 c30 FA y2 x2 s21 1 c31 FA y3 x3 s30 c40 FA y3 x3 s31 1 c41 Note: no speculation of two options in bit 0, since CIN is known.
#8
FA y0 x0 s0 CIN C1 FA y1 x1 s10 c20 FA y1 x1 s11 1 c21 FA y2 x2 s20 c30 FA y2 x2 s21 1 c31 FA y3 x3 s30 c40 FA y3 x3 s31 1 c41 s30 s31 S30-new c40 c41 c40-new
c30
s30 s31 S31-new c40 c41 c41-new
c31
s10 s11 S10-new c20 c21 c20-new
C1
#9
Levels 1 through 3 (complete): see Conditional Sum Adder handout
#10
…see Conditional Sum Adder Handout for complete detailed design