Systems Ripple Carry Adder Shankar Balachandran* Associate - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 9 Module 50

Ripple Carry Adder

Ripple Carry Adder 2

Adders and Subtracters

 The most basic arithmetic operation in a digital computer is

addition.

 Half Adder is a combination circuit that performs addition of 2

bits.

Inputs Outputs a b Carry Sum 1 1 1 1 1 1 1

b a Carry b a b a b a Sum     

Ripple Carry Adder 3

Half Adder

 Half adders cannot accept a carry input and hence it is not possible

to cascade them to construct an n-bit binary adder.

b a Carry b a b a b a Sum     

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Full Adder

 Full Adder is a combinational circuit that forms the arithmetic sum of

three input bits. It is described by the following truth table:

Inputs Outputs c b a Cout Sum

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

 

b a c b a c b c a b a C c b a c b a c b a c b a c b a Sum

• ut

            

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Full Adder Implementation - 1

 

b a c b a c b c a b a C c b a c b a c b a c b a c b a Sum

• ut

            

Full Adder (FA)

ci+1 ci si bi ai bi ai ci si ci+1

Full Adder at bit i

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Full Adder Implementation - 2

 A full adder can be implemented using 2 half adders and an OR gate

bi ai ci si ci+1

Full Adder (FA)

ci+1 ci si bi ai

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Performance of a Full Adder

 Use a 2-input NAND gate implementation of a 1-bit full adder.

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Ripple Carry Adder

 4-bit Binary Adder: ( Sum = A + B )  A 4-bit binary adder can be implemented by cascading four 1-bit full

adders as follows:



Inputs: Outputs: A = (a3a2a1a0) B = (b3b2b1b0) Cin = cin = c0 Sum = (s3s2s1s0) Cout = c4

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Performance of an n-bit Ripple Carry Adder

 Carry ripples from input co to output cn  Worst case propagation delay for sum in terms of 2-input NAND gate

delay (1 gd) is given by,

 Worst case propagation delay for carry output is given by,  Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).

 

         

  2 1

4 2 3 2 2 5 3 2 5

n i sum

n n t        

   2 1 1

3 2 2 2 5 2

n i n carry

n c t for delay

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Exercises

 Design a signed comparator for comparing two 4-bit 1’s

complement numbers A and B

 If A > B, the circuit should produce 1 as output, otherwise 0

 Design a signed comparator for comparing two 4-bit 2’s

complement numbers A and B

 If A > B, the circuit should produce 1 as output, otherwise 0

 Design an n-bit absolute (ABS) value generator for 2’s

complement represented numbers, i.e., for an n-bit input, X, the output is |X|

End of Week 9: Module 50

Thank You

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