Verifying Centaur’s Floating Point Adder
Sol Swords sswords@cs.utexas.edu April 23, 2008
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Verifying Centaurs Floating Point Adder Sol Swords sswords@cs.utexas.edu April 23, 2008 Sol Swords () Verifying Centaurs Floating Point Adder April 23, 2008 1 / 21 Problem Given: Verilog RTL for the Centaur CN processors FADD
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Dependency Checking Functional Sim ulation Delay Modeling
GIFY
BDDify
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Spec side
Dependency Checking Functional Sim ulation Delay Modeling
GIFY
BDDify
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Spec side
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Input BDD Generation
Dependency Checking Functional Sim ulation Delay Modeling
GIFY
BDDify
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Input BDD Generation
◮ We have built them for the single-precision case: 2-4 hours
◮ Also makes it easier to eliminate irrelevant intermediate computations
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Input BDD Generation
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Input BDD Generation
Denorms, Zeros NaNs, Infinities
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Input BDD Generation
GIFY
Q-PARAM
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Input BDD Generation
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Input BDD Generation
◮ evaluate to values satisfying P for all variable settings ◮ are general enough so that every set of values satisfying P can be
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Input BDD Generation
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Input BDD Generation
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Model Side
Dependency Checking Functional Sim ulation Delay Modeling
GIFY
BDDify
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Model Side
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Model Side
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Model Side
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Model Side
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Model Side
◮ More conservative, faster: Use pairs of BDDs to represent upper and
◮ Less conservative, slower: Associate each too-large BDD created with a
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Results
◮ Single-precision: 8 minutes to verify ◮ Double/extended precision: 1 hour each
◮ Fight our way toward an ACL2 theorem. ◮ Prove that we really have a proof. ◮ Need a logical story for Gification. ◮ Adapt the approach to other kinds of hardware. ◮ Need to decompose the problem in other ways than by case-splitting on
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