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Energy Efficient Com puting in Nanoscale CMOS Vivek De Intel - - PowerPoint PPT Presentation
Energy Efficient Com puting in Nanoscale CMOS Vivek De Intel - - PowerPoint PPT Presentation
Energy Efficient Com puting in Nanoscale CMOS Vivek De Intel Fellow Director of Circuit Technology Research Intel Labs I nternet of Everything ( I oE) 2 2 Moores Law scaling 3 Dynam ic platform control 4 4 Near Threshold Voltage (
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Moore’s Law scaling
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Dynam ic platform control
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Near Threshold Voltage ( NTV) com puting
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NTV I A processor
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NTV design techniques
Narrow m uxes No stack height > 2 Robust level converters
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NTV I A – pow ered by solar cell!
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Pow er perform ance m easurem ents
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Pow er com ponents
Logic Dynamic Power Logic Leakage Power Memory Dynamic Power Memory Leakage Power
81% 11% 3% 5% 53% 27% 15% 5% 4% 33% 62% 1%
Logic Vcc: 1.2V Memory Vcc: 1.2V Vcc-max (Super-Threshold) Vcc-opt (Near-Threshold) Vcc-min (Sub-Threshold) Logic Vcc: 0.45V Memory Vcc: 0.55V Logic Vcc: 0.28V Memory Vcc: 0.55V
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Minim um energy operation
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NTV and variability
100 1000 100 200 300 400 500 600 700 800 900 1000 Fast Medium Slow
Leakage Comparison Slow 1.0X Medium 2.5X Fast 7.5X
Frequency (MHz) Energy/Cycle (pJ) 16% 30% 22% 28% 18% 32nm CMOS, 25oC
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Voltage-frequency m argins
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Dynam ic adaptation & reconfiguration
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Dynam ic V & F adaptation
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Resilient platform s
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Resilient & adaptive core
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Perform ance & efficiency gains
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I ntegrated voltage regulators
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Fully integrated VR
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Energy efficient interconnects
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Mem ory capacity & bandw idth
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Efficient & scalable neurom orphic system s
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Efficient & scalable neurom orphic architecture
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The next big leap…
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