Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology - - PowerPoint PPT Presentation

Nanoscale III-V CMOS

• J. A. del Alamo

Microsystems Technology Laboratories Massachusetts Institute of Technology

SEMI Advanced Semiconductor Manufacturing Conference Saratoga Springs, NY; May 16-19, 2016

Acknowledgements:

• Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao
• Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop

Grumman, NSF, Samsung

• Labs at MIT: MTL, EBL

Contents

1. Motivation: Moore’s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Nanowire InGaAs MOSFETs 5. InGaSb p-type MOSFETs 6. Conclusions

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• 1. Moore’s Law at 50: the end in sight?

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Moore’s Law

Moore’s Law = exponential increase in transistor density

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Intel microprocessors

Moore’s Law

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?

How far can Si support Moore’s Law?

Transistor scaling  Voltage scaling  Performance suffers

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Transistor current density:

Transistor performance saturated in recent years

Intel microprocessors Intel microprocessors

Supply voltage:

Chip Price vs. Chip Cost

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Chip area cost:

Increasing chip cost might bring the end to Moore’s Law

Intel microprocessors

Chip area price:

Holt, ISSCC 2016

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Moore’s Law: it’s all about MOSFET scaling

Enhanced gate control  improved scalability

• 1. New device structures:

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Moore’s Law: it’s all about MOSFET scaling

• 2. New materials:

n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb

Future CMOS might involve:

• two different channel materials
• with two different relaxed

lattice constants!

del Alamo, Nature 2011 (updated)

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III-V electronics in your pocket!

• 2. Self-aligned Planar InGaAs MOSFETs

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Lin, IEDM 2012, 2013, 2014 W Mo Lee, EDL 2014; Huang, IEDM 2014 selective MOCVD Sun, IEDM 2013, 2014 Chang, IEDM 2013 reacted NiInAs dry-etched recess implanted Si + selective epi

Self-aligned Planar InGaAs MOSFETs @ MIT

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Lin, IEDM 2012, 2013, 2014

Recess-gate process:

• CMOS-compatible
• Refractory ohmic contacts (W/Mo)
• Extensive use of RIE

W Mo

Fabrication process

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• Ohmic contact first, gate last
• Precise control of vertical (~1 nm), lateral (~5 nm) dimensions
• MOS interface exposed late in process

W/Mo n+ InGaAs/InP InGaAs/InAs InAlAs SiO2 InP -Si Resist Mo Pad HfO2

Mo/W ohmic contact + SiO2 hardmask SF6, CF4 anisotropic RIE CF4:O2 isotropic RIE Cl2:N2 anisotropic RIE Digital etch

Waldron, IEDM 2007

Finished device

Lin, EDL 2014

O2 plasma H2SO4

Mo Nanoscale Contacts

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• Need low c and m  Mo best contact system
• Average c = 0.69 .m2

Mo on n+-In0.53Ga0.47As:

Lu, EDL 2014 Rc ~ 40 Ω.μm for Lc ~ 20 nm

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Lin, IEDM 2013

Lg = 20 nm, Laccess= 15 nm MOSFET  tightest III-V MOSFET made at the time

Lg=20 nm InGaAs MOSFET

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lg=20 nm Ron=224 m 0.4 V

Id (mA/m) Vds (V)

Vgs-Vt= 0.5 V

• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As
• Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)

Highest performance InGaAs MOSFET

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Lg=70 nm:

• Record gm,max = 3.45 mS/m at Vds= 0.5 V
• Ron = 190 m

Lin, EDL 2016

3.45 mS/m

Benchmarking: gm in MOSFETs vs. HEMTs

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MIT MOSFETs

– InGaAs MOSFETs now superior to InGaAs HEMTs – No sign of stalling  more progress ahead!

gm of InGaAs MOSFETs vs. HEMTs (any VDD, any Lg):

del Alamo, J-EDS 2016

Excess OFF-state current

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OFF-state current enhanced with Vds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL)

Lin, IEDM 2013

• 0.6 -0.4 -0.2 0.0

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• 9

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• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

Transistor fails to turn off:

Vds ↑

• 0.4 -0.2 0.0 0.2

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• 11

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• 9

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• 7

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• 5

W/ BTBT+BJT W/O BTBT Vds=0.3~0.7 V step=50 mV

Id (A/m) Vgs (V)

Excess OFF-state current

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Lg↓  OFF-state current ↑  additional bipolar gain effect due to floating body

Lin, EDL 2014

• 0.6 -0.4 -0.2 0.0

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• 11

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• 9

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• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

• 0.6 -0.4 -0.2 0.0

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• 8

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• 7

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• 5

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500 nm 280 nm 120 nm T=200 K Vds=0.7 V

Id (A/m) Vgs-Vt (V)

Lg=80 nm

Vds ↑

Simulations

w/ BTBT+BJT w/o BTBT+BJT

Lg=500 nm

Lin, TED 2015

Planar MOSFET scaling limit

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• Nearly ideal electrostatic scaling behavior
• At limit of scaling around Lg~50 nm

del Alamo, J-EDS 2016

Scaling of linear subthreshold swing

λ =electrostatic scaling length

ideal scaling

• 3. InGaAs FinFETs

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Intel Si Trigate MOSFETs

Bottom-up InGaAs FinFETs

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Si

Waldron, VLSI Tech 2014 Aspect-Ratio Trapping Fiorenza, ECST 2010 Epi-grown fin inside trench

Top-down InGaAs FinFETs

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Kim, IEDM 2013

60 nm

dry-etched fins Radosavljevic, IEDM 2010

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

InGaAs FinFETs: gm

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Thathachary, VLSI 2015

gm per width of gate periphery

• Narrowest InGaAs FinFET fin: Wf=25 nm
• Best fin aspect ratio of InGaAs FinFET: 1
• gm much lower than planar InGaAs MOSFETs

Oxland, EDL 2016 Radosavljevic, IEDM 2011 Kim, IEDM 2013 Natarajan, IEDM 2014

channel aspect ratio

InGaAs FinFETs @ MIT

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Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width
• Aspect ratio > 20
• Vertical sidewalls

InGaAs Double-Gate MOSFET

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Vardi, VLSI 2016

• CMOS compatible process
• Mo contact-first process
• Fin mask left in place  double-gate MOSFET

• gm=1.12 mS/µm
• Ron=230 Ω.µm
• Ssat=140 mV/dec

InGaAs Double-Gate MOSFET

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Vardi, VLSI 2016

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 VGS=0.25 V

• 0.5 V

VGS=0.75 V Id [mA/m] VDS [V] Lg=30 nm Wf=17 nm

• 0.6 -0.4 -0.2 0.0

0.2 0.4 0.6 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 VGS [V] Id [Am] Lg=30 nm Wf=17 nm VDS=500 mV 50 mV Ssat=140 mV/dec DIBL=220 mV/V

Lg=30 nm, Wf=17 nm, Hc=40 nm (AR=2.3):

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57

MIT InGaAs FinFETs

5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

InGaAs FinFETs: gm benchmarking

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gm per width of gate periphery

• First InGaAs FinFETs with Wf<10 nm
• First InGaAs FinFETs with channel aspect ratio >1

20 40 60 5 10 15 20

0.57 0.8 5.7 3.3 2.31.8

MIT InGaAs FinFETs InGaAs FinFETs

5.3 4.3

Si FinFETs

gm/Wf [mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

InGaAs FinFETs: gm benchmarking

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Figure-of-merit for density: gm per fin width

• Improved by 50% over earlier InGaAs FinFETs
• Still far below Si FinFETs  poor sidewall charge control

InGaAs FinFETs: electrostatics

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Linear subthreshold swing scaling:

Close to ideal scaling reveals good quality sidewalls ideal scaling

del Alamo, J-EDS 2016

λc =electrostatic scaling length

Impact of fin width on VT

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• Strong VT sensitivity for Wf < 10 nm; much worse than Si
• Due to quantum effects

InGaAs doped-channel FinFETs: 50 nm thick, ND~1018 cm-3 Oxide: Al2O3/HfO2 (EOT~3 nm) Vardi, IEDM 2015

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• 4. Nanowire InGaAs MOSFETs

Waldron, EDL 2014 Tomioka, Nature 2012 Persson, EDL 2012

• Nanowire MOSFET: ultimate scalable transistor
• Vertical NW: uncouples footprint scaling from Lg and Lc scaling

Tanaka, APEX 2010

InGaAs Vertical Nanowires on Si by direct growth

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Björk, JCG 2012 Selective-Area Epitaxy Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014

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InGaAs VNW-MOSFETs fabricated via top-down approach @ MIT

Zhao, IEDM 2013

Top-down approach: flexible and manufacturable

n+ InGaAs, 70 nm i InGaAs, 80 nm n+ InGaAs, 300 nm

Starting heterostructure:

n+: 6×1019 cm‐3 Si doping

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Key enabling technologies: RIE + digital etch

• Sub-20 nm NW diameter
• DE shrinks NW diameter

by 2 nm per cycle

• Aspect ratio > 10
• Smooth sidewalls

Zhao, EDL 2014

• RIE = BCl3/SiCl4/Ar chemistry
• Digital Etch (DE) =

self-limiting O2 plasma oxidation + H2SO4 oxide removal

RIE + 5 cycles DE

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Optimized RIE + Digital Etch

• Sub-20 nm resolution
• Aspect ratio = 16, vertical sidewall
• Smooth sidewall and surface

15 nm 240 nm

Zhao, EDL 2014

Process flow

Tomioka, Nature 2012 Persson, DRC 2012

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NW-MOSFET I-V characteristics: D=40 nm

Single nanowire MOSFET:

• Lch= 80 nm
• 3 nm Al2O3 (EOT = 1.5 nm)
• gm,pk=620 μS/μm @ VDS=0.5 V
• Ron=895 Ω.μm

0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 300 350

Bottom electrode as the source (BES)

Vgs=-0.2 V to 0.7 V in 0.1 V step Vds (V)

Id A/m)

Zhao, EDL 2016 (submitted)

• 0.4
• 0.2

0.0 0.2 0.4 10

• 9

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Vds=0.5 V

Vgs(V) Id (A/m)

Vds=0.05 V

S=98 mV/dec, Vds=0.05 V S=110 mV/dec, Vds=0.5 V DIBL = 177 mV/V

• 0.4
• 0.2

0.0 0.2 0.4 100 200 300 400 500 600 700 Vgs(V)

Vds=0.5 V

gm,pk(S/m)

200 400 600 200 400 600 800 1000 1200 1400 Vds=0.5 V

Ssat (mV/dec)

gm,pk (S/m)

Tanaka, APEX 2010

Tomioka, IEDM 2011

Tomioka, Nature 2012 Persson, DRC 2012 Persson, EDL 2010

Zhao, IEDM 2013

Berg, IEDM 2015 This work

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Berg, IEDM 2015

Vertical InGaAs NW-MOSFETs Benchmark

Top‐down approach as good as bottom‐up approach This work

Zhao, 2016 (submitted) Best bottom‐up devices

InGaAs VNW MOSFETs: electrostatics

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Linear subthreshold swing scaling:

Close to ideal scaling reveals good quality sidewalls ideal scaling

del Alamo, J-EDS 2016

λc =electrostatic scaling length

• 5. InGaSb p–type MOSFETs

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Nainani, IEDM 2010 Planar InGaSb MOSFET demonstrations: Takei, Nano Lett. 2012

InGaSb p–type FinFETs at MIT

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Lu, IEDM 2015 Key enabling technology:

• BCl3/N2 RIE
• [digital etch under development]

15 nm fins, AR>13 20 nm fins, 20 nm spacing

• Smallest Wf = 15 nm
• Aspect ratio >10
• Fin angle > 85°
• Dense fin patterns

Si-compatible contacts to p+-InAs

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Lu, IEDM 2015

Ni/Ti/Pt/Al on p+-InAs (circular TLMs): Record ρc: 3.5x10-8 Ω.cm2 at 400oC

InGaSb FinFETs

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Lu, IEDM 2015 Fin mask left in place  double-gate MOSFET Channel: 10 nm In0.27Ga0.73Sb Gate oxide: 4 nm Al2O3 (EOT=1.8 nm) Gate: 45 nm Mo

InGaSb FinFETs

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Lu, IEDM 2015

Wf = 30 – 100 nm Lg = 0.1 – 1 μm Nf = 70

InGaSb FinFET I-V characteristics

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• Lg = 100 nm, Wf = 30 nm (AR=0.33)
• Normalized by conducting gate periphery
• High current
• Poor turn-off

Lu, IEDM 2015

gm benchmarking

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• First InGaSb FinFET
• Peak gm approaches best InGaSb planar MOSFETs

Peak gm at T=290K:

0.01 0.1 1 10 100 10 100

Yuan, 2013 [7] Nainani, 2010 [8] Chu, 2014 [11] Xu, 2011 [12] Nagaiah, 2011 [13]

In0.36Ga0.64Sb GaSb

gm (S/m) Lg (m)

This work (FinFET) In0.27Ga0.73Sb GaSb In0.35Ga0.65Sb In0.2Ga0.8Sb

Planar MOSFETs

Lu, IEDM 2015

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Conclusions

1. Great recent progress on planar, fin and nanowire III-V MOSFETs 2. Planar and multigate InGaAs MOSFETs exhibit nearly ideal electrostatic scaling behavior 3. Device performance still lacking for multigate designs 4. P-type InGaSb MOSFETs promising

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A lot of work ahead but… exciting future for III-V electronics