Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology - PowerPoint PPT Presentation

Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology Laboratories Massachusetts Institute of Technology SEMI Advanced Semiconductor Manufacturing Conference Saratoga Springs, NY; May 16-19, 2016 Acknowledgements: • Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung • Labs at MIT: MTL, EBL

Contents 1. Motivation: Moore’s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Nanowire InGaAs MOSFETs 5. InGaSb p-type MOSFETs 6. Conclusions 2

1. Moore’s Law at 50: the end in sight? 3

Moore’s Law Moore’s Law = exponential increase in transistor density Intel microprocessors 4

Moore’s Law How far can Si support Moore’s Law? ? 5

Transistor scaling  Voltage scaling  Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors Transistor performance saturated in recent years 6

Chip Price vs. Chip Cost Chip area price: Chip area cost: Intel microprocessors Holt, ISSCC 2016 Increasing chip cost might bring the end to Moore’s Law 7

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Moore’s Law: it’s all about MOSFET scaling 1. New device structures: Enhanced gate control  improved scalability 9

Moore’s Law: it’s all about MOSFET scaling 2. New materials: n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb Future CMOS might involve: • two different channel materials • with two different relaxed lattice constants ! del Alamo, Nature 2011 (updated) 10

III-V electronics in your pocket! 11

2. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM 2013 12

Self-aligned Planar InGaAs MOSFETs @ MIT W Mo Lin, IEDM 2012, 2013, 2014 Recess-gate process: • CMOS-compatible • Refractory ohmic contacts (W/Mo) • Extensive use of RIE 13

Fabrication process Mo/W ohmic contact CF 4 :O 2 isotropic RIE SF 6 , CF 4 anisotropic RIE + SiO 2 hardmask Resist SiO 2 W/Mo n + InGaAs/InP InP InGaAs/InAs  -Si InAlAs Waldron, IEDM 2007 Digital etch Finished device Cl 2 :N 2 anisotropic RIE O 2 plasma H 2 SO 4 Pad Mo HfO 2 Lin, EDL 2014 • Ohmic contact first, gate last • Precise control of vertical (~1 nm), lateral (~5 nm) dimensions • MOS interface exposed late in process 14

Mo Nanoscale Contacts Mo on n + -In 0.53 Ga 0.47 As: R c ~ 40 Ω.μm for L c ~ 20 nm Need low  c and  m  Mo best contact system • Average  c = 0.69  .  m 2 • Lu, EDL 2014 15

L g =20 nm InGaAs MOSFET 1.0 V gs -V t = 0.5 V L g =20 nm R on =224  m 0.8 0.4 V I d (mA/  m) 0.6 0.4 0.2 0.0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) L g = 20 nm, L access = 15 nm MOSFET  tightest III-V MOSFET made at the time Lin, IEDM 2013 16

Highest performance InGaAs MOSFET • Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As • Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) 3.45 mS/  m L g =70 nm: Record g m,max = 3.45 mS/  m at V ds = 0.5 V • R on = 190  m • Lin, EDL 2016 17

Benchmarking: g m in MOSFETs vs. HEMTs g m of InGaAs MOSFETs vs. HEMTs (any V DD , any L g ): MIT MOSFETs del Alamo, J-EDS 2016 – InGaAs MOSFETs now superior to InGaAs HEMTs – No sign of stalling  more progress ahead! 18

Excess OFF-state current Transistor fails to turn off: L g =500 nm -5 10 V ds ↑ I d (A/  m) -7 10 -9 10 V ds =0.3~0.7 V step=50 mV -11 10 -0.6 -0.4 -0.2 0.0 V gs (V) OFF-state current enhanced with V ds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013 19

Excess OFF-state current L g =500 nm -5 10 -4 10 T=200 K V ds ↑ V ds =0.7 V -5 I d (A/  m) 10 -7 10 I d (A/  m) -6 10 L g =80 nm -9 10 -7 10 120 nm V ds =0.3~0.7 V 280 nm step=50 mV -8 10 -11 10 500 nm -0.6 -0.4 -0.2 0.0 V gs (V) -0.6 -0.4 -0.2 0.0 V gs -V t (V) Simulations W/ BTBT+BJT w/ BTBT+BJT -5 10 W/O BTBT w/o BTBT+BJT Lin, EDL 2014 L g =500 nm I d (A/  m) Lin, TED 2015 -7 10 -9 10 L g ↓  OFF-state current ↑ V ds =0.3~0.7 V  additional bipolar gain effect due to step=50 mV -11 10 -0.4 -0.2 0.0 0.2 floating body V gs (V) 20

Planar MOSFET scaling limit Scaling of linear subthreshold swing del Alamo, J-EDS 2016 ideal scaling λ =electrostatic scaling length • Nearly ideal electrostatic scaling behavior • At limit of scaling around L g ~50 nm 21

3. InGaAs FinFETs Intel Si Trigate MOSFETs 22

Bottom-up InGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech 2014 23

Top-down InGaAs FinFETs dry-etched fins Radosavljevic, IEDM 2010 60 nm Kim, IEDM 2013 24

InGaAs FinFETs: g m g m per width of gate periphery Natarajan, Radosavljevic, 2.0 IEDM 2014 IEDM 2011 0.18 Si FinFETs 5.3 0.23 0.66 4.3 1.5 channel 1 aspect 0.57 g m [mS/  m] ratio Kim, IEDM 2013 1.0 0.63 0.6 0.5 0.8 InGaAs FinFETs 0.0 0 20 40 60 W f [nm] Oxland, EDL 2016 Thathachary, VLSI 2015 • Narrowest InGaAs FinFET fin: W f =25 nm • Best fin aspect ratio of InGaAs FinFET: 1 • g m much lower than planar InGaAs MOSFETs 25

InGaAs FinFETs @ MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch • Sub-10 nm fin width Vardi, DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 26

InGaAs Double-Gate MOSFET Vardi, VLSI 2016 • CMOS compatible process • Mo contact-first process • Fin mask left in place  double-gate MOSFET 27

InGaAs Double-Gate MOSFET L g =30 nm, W f =17 nm, H c =40 nm (AR=2.3): 1.0 1E-3 L g =30 nm V GS =0.75 V V DS =500 mV W f =17 nm 0.8 1E-4 50 mV 0.6 1E-5 I d [mA/  m]  V GS =0.25 V I d [A  m] S sat =140 mV/dec 0.4 1E-6 DIBL=220 mV/V L g =30 nm 0.2 1E-7 -0.5 V W f =17 nm 0.0 1E-8 0.0 0.2 0.4 0.6 0.8 1.0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V DS [V] V GS [V] • g m =1.12 mS/µm • R on =230 Ω.µm • S sat =140 mV/dec Vardi, VLSI 2016 28

InGaAs FinFETs: g m benchmarking g m per width of gate periphery 2.0 0.18 Si FinFETs 5.3 0.23 0.66 4.3 1.5 1 0.57 1.8 g m [mS/  m] MIT 2.3 1.0 InGaAs FinFETs 0.63 3.3 0.6 0.5 0.8 5.7 InGaAs FinFETs 0.0 0 20 40 60 W f [nm] • First InGaAs FinFETs with W f <10 nm • First InGaAs FinFETs with channel aspect ratio >1 29

InGaAs FinFETs: g m benchmarking Figure-of-merit for density: g m per fin width 20 5.3 Si FinFETs 15 4.3 g m /W f [mS/  m] MIT 10 InGaAs FinFETs InGaAs FinFETs 5 1 3.3 2.31.8 0.66 0.18 0.23 0.57 0.63 0.6 0.8 5.7 0 0 20 40 60 W f [nm] • Improved by 50% over earlier InGaAs FinFETs • Still far below Si FinFETs  poor sidewall charge control 30

InGaAs FinFETs: electrostatics Linear subthreshold swing scaling: del Alamo, J-EDS 2016 ideal scaling λ c =electrostatic scaling length Close to ideal scaling reveals good quality sidewalls 31

Impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Oxide: Al 2 O 3 /HfO 2 (EOT~3 nm) • Strong V T sensitivity for W f < 10 nm; much worse than Si • Due to quantum effects Vardi, IEDM 2015 32

4. Nanowire InGaAs MOSFETs Waldron, EDL 2014 Tanaka, APEX 2010 Persson, EDL 2012 Tomioka, Nature 2012 • Nanowire MOSFET: ultimate scalable transistor • Vertical NW: uncouples footprint scaling from L g and L c scaling 33

InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Selective-Area Epitaxy Vapor-Solid-Liquid (VLS) Technique Riel, MRS Bull 2014 Björk, JCG 2012 34

InGaAs VNW-MOSFETs fabricated via top-down approach @ MIT Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : 6 × 10 19 cm ‐3 Si doping Top-down approach: flexible and manufacturable Zhao, IEDM 2013 35

Key enabling technologies: RIE + digital etch • RIE = BCl 3 /SiCl 4 /Ar chemistry • Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal RIE + 5 cycles DE • Sub-20 nm NW diameter • DE shrinks NW diameter by 2 nm per cycle • Aspect ratio > 10 • Smooth sidewalls Zhao, EDL 2014 36

Optimized RIE + Digital Etch 15 nm 240 nm Zhao, EDL 2014 • Sub-20 nm resolution • Aspect ratio = 16, vertical sidewall • Smooth sidewall and surface 37

Process flow Tomioka, Nature 2012 Persson, DRC 2012 38

NW-MOSFET I-V characteristics: D=40 nm V gs =-0.2 V to 0.7 V in 0.1 V step 350 700 Bottom electrode as the source (BES) 300 V ds =0.5 V 600 250 I d  A/  m) 500 200 g m,pk (  S/  m ) 400 150 300 100 200 50 100 0 0.0 0.1 0.2 0.3 0.4 0.5 0 V ds (V) -0.4 -0.2 0.0 0.2 0.4 V ds =0.5 V V gs (V) Single nanowire MOSFET: -4 10 -5 • L ch = 80 nm 10 V ds =0.05 V I d ( A/  m ) -6 10 • 3 nm Al 2 O 3 (EOT = 1.5 nm) S=98 mV/dec, V ds =0.05 V -7 10 • g m,pk =620 μS/μm @ V DS =0.5 V S=110 mV/dec, V ds =0.5 V -8 10 DIBL = 177 mV/V • R on =895 Ω.μm -9 10 -0.4 -0.2 0.0 0.2 0.4 V gs (V) Zhao, EDL 2016 (submitted) 39