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JST - DFG Joint Workshop January 21, 2009 Atomic level material processing and characterization for nanoscale CMOS transistors Toshihiko Kanayama Nanodevice Innovation Research Center, AIST, Japan MIRAI project 1 New Materials and Structures


  1. JST - DFG Joint Workshop January 21, 2009 Atomic level material processing and characterization for nanoscale CMOS transistors Toshihiko Kanayama Nanodevice Innovation Research Center, AIST, Japan MIRAI project 1

  2. New Materials and Structures for Ultra-scaled MOSFET Structure evolution for gate control Gate SiGe Strained Si 、 SiGe メタル ゲート SiO 2 、 High-k Gate Source Drain Source Drain BOX 埋め込み酸化膜 BOX Si Strained SOI 、 SGOI FET Planar FET Multi-gate FET Materials evolution for high drive current Present Future High-mobility Materials → Channel Si ( Strained Si, SiGe, Ge) High-k Dielectrics → Gate Dielectrics SiO 2 (SiON) (HfSiO, HfAlO, LaAlO) → Gate Electrode Poly-Si Metal, Metal Silicide → Source/Drain Si SiGe, SiC, MSi x , MGe x Keeping Ioff low and enhancing Ion by optimal selection of materials and structures 2/24

  3. Increasing Requirements for Metrology and Characterization Technology Size variation CD & LER Porous Low-k Side wall roughness reliability issue Metal Gate Pore size, connectivity Metal S/D Mechanical strength High-k Cu Voiding due to Stress/ Electro migration Dopant diffusion and fluctuation Strained Si, SiGe Strain distribution Potential/Dopant distribution Major Issues • Technology boosters, i.e., new materials/structures and processes are rushing into semiconductor technology. • Variability increases. To implement new technologies while minimizing variation, reliable characterization and metrology technologies are crucially needed. 3/24

  4. Contents For the fabrication of Nano CMOS Transistors What do we need? • Gate stack (Gate dielectrics and electrode) • Channel • Source/Drain 4/24

  5. Towards EOT (equivalent oxide thickness) =0.5nm Gate CC-D&A* Gate Electrode I leak NiSi Deposition Anneal Drain Source 1 Cycle 750 ℃ HfO 2 HfO 2 I on Interfacial Si HfSiO x layer Si Si LSTP( LSTP( hp 45,32,22) hp 45,32,22) LOP( LOP( hp 45,32,22) hp 45,32,22) Si 2 2 10 10 Gate Leakage Current 【A/cm 2 】 SiO 2 Cycle-by-Cycle This technique Deposition & Annealing 1 : MIRAI : MIRAI -2 -2 Other 10 10 organizations NiSi -4 -4 10 10 HfO 2 HfSiO x HfAlON HfAlON -6 -6 10 10 0.4nm HfSiON Si 1nm -8 -8 10 10 0.5 0.5 1.0 1.0 1.5 1.5 2.0 2.0 2.5 2.5 3.0 3.0 A. Ogawa et al., INFOS (2007) equivalent oxide thickness【nm】 5/24

  6. Control of threshold voltage Fermi Level Pinning Gate Gate V FB (V) Top : HfO 2 Bottom : Al 2 O 3 NiSi Top high-k Al 2 O 3 Bottom high-k SiO 2 0.4 Al 2 O 3 Si Top : Al 2 O 3 HfO 2 Bottom : HfO 2 0.2 Energy Offset HfO 2 0 Si 0 0.5 1.0 1.5 2.0 Dipole Thickness of bottom high-k film (nm) formation Iwamoto, VLSI Symp. 2007 6/24

  7. Contents For the fabrication of Nano CMOS Transistors What do we need? • Gate stack (Gate dielectrics and electrode) • Channel: Surface flatness G S D Multi-Gate (Nanowire) Transistor 7/24

  8. Atomically flattening of Si surfaces AFM measurement of Sidewall roughness Si(001) Si(110) 200nm □ Si(111) Low pH HF treatment + Hydrogen anneal ( 800 ℃) Line profile H 2 annealed : 800 ℃ , 0.1 torr, 40 s Before H 2 anneal ( after RIE ) (SPM + RCA+ LPH + H 2 anneal) 8/24

  9. Atomic Precision CD Metrology by AFM Sidewall and line edge roughness measured CD-AFM with Laser interferometer by tilt-step-in operation Modularized Laser interferometer Resolution 0.05 nm � 3D AFM scanner: parallel spring mechanism. � Laser interferometer: DSP-based processing. 9 Displacement (nm) 8 7 0.1 nm 0.05 nm 6 X (nm) 20 H=400nm 10 0.25 nm 5 Size of hydrogen 0 0 20 40 60 80 100 atom Y (nm) 4 Z X (nm) 20 H=200nm Y 0 0.5 1.0 1.5 2.0 10 Time (sec) X 0 0 20 40 60 80 100 ArF resist/ 240 nm S. Gonda et al., Characterization and Y (nm) Metrology for ULSI Tech., 2005 Low-k patterns K. Murayama et al, SPIE, 2006 9/24

  10. Surface hydrophilicization (a) HF-treatment (oxide removal, H-termination) H H O (b) RTA 700 ˚ C (N 2 1torr: H-desorption) H H (c) H 2 O exposure 250 ˚ C (Formation of Si-OH) H H O O H H H H H H Si sub. Si sub. Si sub. (b) H-desorption (c) Hydrophilicized surface (a) H-terminated surface 700 ˚ C N2 H 2 O exposure 250 ˚ C 1.0E+02 1.2 Hydrophilicized 1 Jg@V FB -1V (A/cm 2 ) 1.0E+01 NiSi HF-last 0.8 EOT (nm) 1.0E+00 0.6 HfO 2 0.4 Al 2 O 3 1.0E-01 0.2 Si Hydrophilicized 0 1.0E-02 0 2 4 6 8 10 0 2 4 6 8 10 Inserted Al 2 O 3 cycles Morita, SSDM 2008 Inserted Al 2 O 3 cycles 10/24

  11. Ge-pMOSFET with Lg=60nm Si passivation for Gate stack, NiGe Metal S/D Velocity 500 7ML Si Epi-layer Quasi-ballistic transport G M SAT Max. (mS/mm) C OX V SAT Ge V SAT Ge = 6E6cm/s 100 slope 1/ L G 50 V D = -1.0V Channel conc. : 4.4E15cm -3 : 1.3E17cm -3 : 3.3E17cm -3 10 : 7.0E17cm -3 5 TaN TaN 100 1000 10000 NiGe NiGe NiGe NiGe Gate length L G (nm) n-Ge n-Ge Yamamoto et al. IEDM, 2007 50nm 50nm 11/24

  12. Uni-axially Strained Multi-Gate CMOS Transistors nMOSFET pMOSFET Uni-axial tensile strain on Si (110) surface Uni-axial Compressive strain on SiGe (110) surface <110> NiSi <110> SiN pMOS 50 nm 50 nm Gate Poly-Si Poly Poly 45 nm 45 nm SSOI SSOI (100) (001) 55 nm 90 nm Gate (110) (110) SiGe BOX BOX SiO 2 SSOI SGOI 0.08 0.35 L g = 0.4 μm SGOI Fin (110) Vd = 0.05 V 0.07 SSOI Tri-gate Uniaxially strained V d = -50 mV 0.3 Lg = 10 μ m 0.06 Gm x Tox / W (mS) Wfin = 50 nm 0.25 0.05 gm ( μ S) Id // <110> 0.2 0.04 2.2x ×3 0.15 0.03 0.1 0.02 0.01 SOI Planar SOI Tri-gate 0.05 (100) Unstrained 0 0 -2 -1.5 -1 -0.5 0 0.5 -0.5 0 0.5 1 1.5 2 Vg (V) Vg-Vth (V) T. Irisawa et al. IEDM, 2006 T. Irisawa et al., IEDM, 2005 12/24

  13. NBD (NanoBeam electron Diffraction) Z Z-axis X Tensile strain X-axis Si(x,z) =(5.474 Å ,5.417 Å ) St-Si 17nm St-Si SiGe(x,z)=(5.469 Å ,5.504 Å ) SiGe 35nm SiGe e - -beam 100nm Box Si sub. Usuda, Materials Sci. Eng. Si(x,z)=(5.433 Å ,5.433 Å ) Si B124–125 (2005) 143 70nm Poly-Si Strained-Si Relaxed- SiGe buffer Lg=1 μ m layer Strain in a MOSFET channel 13/24

  14. Confocal/probe-excited UV Raman microscope for local strain analysis 1 μ m To spectrometer λ = 364 nm SiO 2 λ = 675 nm for AFM Position- Si sensitive detector × 10 3 Raman Shift (1/cm) AFM probe Excitation y μ m λ=364 nm, φ~130 nm Raman scattering weak strong Compressive stress Raman shift : Si x μ m 1/λ out - 1/λ in SiO 2 = phonon vibration 2D Raman mapping For strain ε in Si Δ ( 1/λ ) = 723 ε cm -1 Poborchii, Appl. Phys. Lett. 89 (2006) 233505 14/24

  15. Raman Measurements on (110) Cross Section of STI Structure Polarization (110) Cross Section (Excitation/Detection) Doublet ☆ (a/b) [001] b Δω d SiO 2 Singlet ☆ (a/a) 520.5 cm -1 [110] a Δω s Si [ 001 ] Uniaxial [1-10] c ☆ (a/b) I 3 Δω 3 ☆ (a/a) I 2 800 σ Stress (MPa) [110] Δω 2 xx ( c/b ) 520.5 cm -1 I 1 600 Δω 1 [ 110 ] Uniaxial 400 σ 521.23 zz [001] 200 2000 aa ab Intensity, a.u. 1500 0 50000 50500 51000 51500 Position (nm) 1000 Trench Bottom 520.85 Resolving Axial Components 500 Tada, SSDM 2008 0 Δω ab =C 1 σ( 100 )+ C 2 σ( 110 ) 515 520 525 530 Δω ab =C 3 σ( 100 )+ C 4 σ( 110 ) -1 Raman Shift, cm 15/24

  16. Contents For the fabrication of Nano CMOS Transistors What do we need? • Gate stack (Gate dielectrics and electrode) • Channel: Surface flatness, high-mobility material, Local strain • Source/Drain: Dopant profiling for ultra-shallow junction, metal source/drain 16/24

  17. Simultaneous measurement of potential and individual dopant atoms I-V STM Probe Donor distribution correlates Cross Section of MOSFET with the potential fluctuation. Tunneling Current Gate n: As 10 keV, p: B 10 keV 5x10 13 cm -2 1.5x10 13 cm -2 Source Drain V s = +1.7 V, I t = 6 pA 40 nm p n Key process Flattening and hydrogenation of (111) surface by NH 4 F treatment followed by dopant reactivation at ~400°C Imaging of dopant atoms acceptor donor V s Substrate bias voltage: V s negative charge positive charge V s >0 donors (red spot) acceptors (blue spot) V s <0 Kanayama, A-3-1 Nishizawa, Appl. Phys. Lett. 90 (2007) 122118. 40 nm 17/24

  18. Local Work Function Measurements on a Transistor Cross Section 0.5 × 0.5 μ m 2 500 500 Y 400 400 Y: Gate Edge Position (nm) Position (nm) 300 300 G G G G 90 nm 90 nm 200 200 D D D D X 100 100 Lg=35 nm 0 0 (b) Local Work Function 3 3 2 2 1 1 0 0 (dI/dZ ) (arb.u.) (dI/dZ ) (arb.u.) Channel (dI/dZ) (arb.u.) 3 170 nm Vacuum-Gap Modulation 2 ⇨ local work function ∝ d I /d z S D 1 dV Z 0 V Z dI 0 100 200 300 400 500 STM Position (nm) A probe X: 30 nm below surface Vo ultra-thin oxide dZ Zo SiO 2 S/D : 35keV As 2 × 10 15 cm -2 Si Bolotov, SSDM 2008 18/24

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