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Efficient FPGA implementation of a Digital Transparent Satellite Processor G. Marini, V. Sulli, F. Santucci, M. Faccio University of LAquila, LAquila, Italy Outline Introduction Problem Definition Resolution Method FPGA

SLIDE 1

Efficient FPGA implementation of a Digital Transparent Satellite Processor

G. Marini, V. Sulli, F. Santucci, M. Faccio

University of L’Aquila, L’Aquila, Italy

SLIDE 2

Outline

Introduction
Problem Definition
Resolution Method
FPGA Implementation
Results
Conclusion
Future Work

SLIDE 3

Introduction(1)

In satellite systems for telecommunications a great deal of interest concerns the mesh topology

[Mesh topology]

SLIDE 4

Introduction(2)

Four alternatives for the architecture of a satellite transponder:

Fully transparent payload
Fully regenerative payload
Digital transparent payload
Digital Semi-transparent payload

SLIDE 5

Introduction(3)

Four alternatives for the architecture of a satell ite transponder:

Fully transparent payload
Fully regenerative payload
Digital transparent payload
Digital Semi-transparent payload

Digital Transparent Processor (DTP) is involved

SLIDE 6

Introduction(4)

Four alternatives for the architecture of a satell ite transponder:

Fully transparent payload
Fully regenerative payload
Digital transparent payload
Digital Semi-transparent payload

Digital Transparent Processor (DTP) is involved

Support of mesh networking
Flexibility in the routing
Frequency planning flexibility

SLIDE 7

Introduction(5)

Scenario of interest:

79 beams (with 125 MHz allocated per

beam) with fully connectivity and flexible routing in frequency, time spatial domains

SLIDE 8

Introduction(6)

In this context the digital semi-transparent payloads have been recently devised and investigated

SLIDE 9

Problem Definition(1)

A digital transparent/semi-transparent

satellite payload can be see as a hybrid analog-digital on-board chain

Modelling and design approaches have

so far almost missed the ability to capture in an adequate way these important features

SLIDE 10

Problem Definition(2)

Problem: To provide a method that, given the link-budget requirement, provides a detailed definition of digital HW components in the DTP

SLIDE 11

Resolution Method(1)

Step 1:

Define a System Model of DTP-based

Transponder

A DTP processing chain is composed by:

P0: ADC
P1: Analytical signal extrapolation
P2: Channalizer (analysis)
Switching
P3: Channalizer (synthesis)
P4: IF signal extrapolation
P5: DAC

SLIDE 12

Resolution Method(2)

Step 2:

Develop an equivalet noise model for the

whole DTP chain to understand how link level performance (the DTP noise figure) may impact on the DTP hardware complexity

SLIDE 13

Resolution Method(3)

Step 3:

Computing the hardware complexity in

terms of:

i. Number of 2-words multipliers
ii. Number of 2-words adders

iii.Number of Flip-Flops iv.Number of ROM bits

SLIDE 14

FPGA Implementation(1)

The DTP is composed by three basic blocks:

FIR filter elements, implemented in direct

form

SLIDE 15

FPGA Implementation(2)

The DTP is composed by three basic blocks:

FIR filter elements, implemented in direct

form

FFT/IFFT butterfly structures

SLIDE 16

FPGA Implementation(3)

The DTP is composed by three basic blocks:

FIR filter elements, implemented in direct

form

FFT/IFFT butterfly structures
RAM buffers

SLIDE 17

Results(1)

To the increase of DTP Noise Figure corresponds a degradation in the link performance show as reduction in the Additional Margin at the ground receiver

SLIDE 18

Results(2)

The DTP Hardware complexity may be directly linked to the chosen working point

SLIDE 19

Results(3)

For a given DTP Noise Figure, different hard- ware complexity can be obtained by applying different design approaches, e.g.:

UP: Uniform Parameters
TO: Trade-Off
UC: Uniform Contributions
MR: Minimum RAM

SLIDE 20

Conclusion

We have developed a comprehensive

framework for hardware complexity evaluation of novel satellite payloads that rely on semi-transparent transponder architectures

The DTP complexity has been related

to the overall processed bandwidth, the selected coding and modulation formats, and performance degradation requirements

SLIDE 21

Future Work

Definition of an optimized criterion for

DTP hardware design

Adaptations of the developed framework

to several scenarios of interest in satellite communications

SLIDE 22

Efficient FPGA implementation of a Digital Transparent Satellite Processor

Outline

Introduction(1)

In satellite systems for telecommunications a great deal of interest concerns the mesh topology

Introduction(2)

Four alternatives for the architecture of a satellite transponder:

Introduction(3)

Four alternatives for the architecture of a satell ite transponder:

Introduction(4)

Four alternatives for the architecture of a satell ite transponder:

Introduction(5)

Scenario of interest:

beam) with fully connectivity and flexible routing in frequency, time spatial domains

Introduction(6)

In this context the digital semi-transparent payloads have been recently devised and investigated

Problem Definition(1)

satellite payload can be see as a hybrid analog-digital on-board chain

so far almost missed the ability to capture in an adequate way these important features

Problem Definition(2)

Problem: To provide a method that, given the link-budget requirement, provides a detailed definition of digital HW components in the DTP

Resolution Method(1)

Step 1:

Transponder

Resolution Method(2)

Step 2:

whole DTP chain to understand how link level performance (the DTP noise figure) may impact on the DTP hardware complexity

Resolution Method(3)

Step 3:

terms of:

iii.Number of Flip-Flops iv.Number of ROM bits

FPGA Implementation(1)

The DTP is composed by three basic blocks:

form

FPGA Implementation(2)

The DTP is composed by three basic blocks:

form

FPGA Implementation(3)

The DTP is composed by three basic blocks:

form

Results(1)

To the increase of DTP Noise Figure corresponds a degradation in the link performance show as reduction in the Additional Margin at the ground receiver

Results(2)

The DTP Hardware complexity may be directly linked to the chosen working point

Results(3)

For a given DTP Noise Figure, different hard- ware complexity can be obtained by applying different design approaches, e.g.:

Conclusion

framework for hardware complexity evaluation of novel satellite payloads that rely on semi-transparent transponder architectures

to the overall processed bandwidth, the selected coding and modulation formats, and performance degradation requirements

Future Work

DTP hardware design

to several scenarios of interest in satellite communications

Thanks