Circuits in Emerging Nanotechnologies Rinaldo Castello University - - PowerPoint PPT Presentation

Circuits in Emerging Nanotechnologies

Rinaldo Castello University of Pavia Thomas Ernst CEA-LETI Seok-Hee Lee SK-Hynix Subhasish Mitra Stanford University Ion O’Connor Ecole Centrale de Lyon Chair: Adrian Ionescu, EPFL

Rinaldo Castello University of Pavia

Thomas Ernst CEA-LETI

FROM INTEGRATED CIRCUITS TO INTEGRATED SYSTEMS

THOMAS ERNST Montreux Symposium on emerging trends in electronics 1/12/2014

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Today The packaging evolution Heterogeneous Era ! Si/Smart Interposers ! Memory on Logic ! Logic on analog ! MEMS on logic ! RF/ANALOG ! 3D imagers ! Biochips 0 -10 years The alternative to “More Moore” scaling ! Logic-on-Logic : (Monolithic and 3D-Stacked) ! Monolithic 3D memories ! PHOTONICS ! RF/MEMS – ANALOG ! Biochips ! Novel substrates

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5- 15 years Advanced concepts ! Novel computing paradigms ! Beyond CMOS hybridization ! Bio-inspired 3D process

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Seok-Hee Lee SK-Hynix

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• 2014. 12. 1

Seok-Hee Lee R&D Division, SK hynix

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Memory demand split across multiple sub-segments

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Low Cost Low Power High Speed

Higher Tr. Performance (High Speed)

Automotive PC / Server Smart Devices Wearable Devices DRAM

Jox [A/cm2] Tox [Å] Nitrided SiO2 Jox Limit for DRAM Tr Jox Limit for Logic Tr HKMG Tox [Å] Gate Length of Peripheral Tr. [nm] [Source : ITRS 2003~2007] Logic Tr DRAM Tr HKMG 25nm node

Transistor for Higher performance & Lower Power

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Low Power DRAM design Technique example

Power Gating Multi-VTH Dynamic Body Bias

Objective Reduce leakage currents by inserting a switch transistor into the logic stack Reduce leakage power where speed is not needed by high Vt transistor Controlling body bias, high speed & lo w leakage current can be achieved Scheme

Vdd Logic Cell Virtual Ground sleep Vdd Logic Cell Switch Cell L L L L L L L L H L L L L L L H Q&(+!"2,,-N!Q&(+!V,$`$(,!

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Solutions for Higher Performance & Higher Density

Density

Conventional Stacking # High Density, Low Performance Non-Stacking # High Performance, Low Density Wire Bonding

Memory Requirements . Lower Power . Higher Performance . Higher Density

[16Gb TSV, SK Hynix : 40nm 2Gb x 8]

Performance

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TSV-Stacking # High Density High performance Low power # but, High Cost & Process Difficulty

High Reliability & Low Cost DRAM

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Item Objective Effect, Status Issues DFR (Design For cell Reliabilit y) Advanced Refresh Refresh Compensate Retention Time Degr adation Increase IDD Smart Refresh Refresh Improve LtRAS VBB Temp Modulation Write Write Recovery Time POD (Post Over Drive) Refresh Compensate Sensing Margin Increase IDD On chip ECC Error Correction Area Overhead PPR (using ARE) Error Aging Fail

Subhasish Mitra Stanford University

The Next 1,000X

Subhasish Mitra Collaborator: H.-S. Philip Wong

Department of EE & Department of CS Stanford University

Abundant-Data Applications

27

N3XT 1,000X Energy Efficiency

28

3D Resistive RAM Massive storage Carbon nanotube FET compute elements STTRAM L2, L3, … Carbon nanotube FET (or even silicon) compute elements

• 1. All data active on-chip
• 2. Computation immersed in memory
• 3. Variability, yield, reliability

Monolithic 3D Inter-layer vias: 1,000X TSV density

thermal thermal

Carbon Nanotube FET (CNFET)

29

CNT: d = 1.2nm

d

CNFET

Sub-litho pitch

• 1. First CNFET computer
• 2. High-performance CNFETs

CNFET (Stanford fab) Si FETs (foundries)

ION (!A/!m)

[Shulaker Nature 13, ISSCC 13, IEDM 14]

First CNT Monolithic 3D IC

30 [Wei IEDM 13, Shulaker VLSI Tech. 14, IEDM 14]

VOUT (V) VIN (V)

1 2 3 1 2 3

Inter-layer digital circuits

Conventional vias, no TSVs Process temp. < 250 oC

CNT

Silicon FETs Resistive RAM CNFETs Logic + memory Resistive RAM

Ian O’Connor Ecole Centrale de Lyon

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Circuits in Emerging Nanotechnologies

Rinaldo Castello University of Pavia Thomas Ernst CEA-LETI Seok-Hee Lee SK-Hynix Subhasish Mitra Stanford University Ion O’Connor Ecole Centrale de Lyon Chair: Adrian Ionescu, EPFL

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Circuits in Emerging Nanotechnologies

Rinaldo Castello University of Pavia Thomas Ernst CEA-LETI Seok-Hee Lee SK-Hynix Subhasish Mitra Stanford University Ion O’Connor Ecole Centrale de Lyon Chair: Adrian Ionescu, EPFL