Chip-8 Emulation on a SoCKit FPGA Team: Ashley Kling, Levi Oliver, - - PowerPoint PPT Presentation

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Chip-8 Emulation on a SoCKit FPGA Team: Ashley Kling, Levi Oliver, - - PowerPoint PPT Presentation

Apr 21, 2023 34 likes •250 views

Chip-8 Emulation on a SoCKit FPGA Team: Ashley Kling, Levi Oliver, Gabrielle Taylor, David Watkins Supervisor: Prof. Stephen Edwards 1 Chip-8 Emulation Overview Not your garden variety interpreted programming language Opcodes and

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SLIDE 1

Chip-8 Emulation

  • n a SoCKit FPGA

Team: Ashley Kling, Levi Oliver, Gabrielle Taylor, David Watkins Supervisor: Prof. Stephen Edwards

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SLIDE 2

1

Chip-8 Emulation Overview

Not your garden variety interpreted programming language

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SLIDE 3

Opcodes and Instructions

▪ Chip-8 has a total of 35 instructions

  • Unsupported
  • Supported
  • Cycle Intensive

00E0 - CLS 00EE - RET 0nnn - SYS addr 1nnn - JP addr 2nnn - CALL addr 3xkk - SE Vx, byte 4xkk - SNE Vx, byte 5xy0 - SE Vx, Vy 6xkk - LD Vx, byte 7xkk - ADD Vx, byte 8xy0 - LD Vx, Vy 8xy1 - OR Vx, Vy 8xy2 - AND Vx, Vy 8xy3 - XOR Vx, Vy 8xy4 - ADD Vx, Vy 8xy5 - SUB Vx, Vy 8xy6 - SHR Vx {, Vy} 8xy7 - SUBN Vx, Vy 8xyE - SHL Vx {, Vy} 9xy0 - SNE Vx, Vy Annn - LD I, addr Bnnn - JP V0, addr Cxkk - RND Vx, byte Dxyn - DRW Vx, Vy, nibble Ex9E - SKP Vx ExA1 - SKNP Vx Fx07 - LD Vx, DT Fx0A - LD Vx, K Fx15 - LD DT, Vx Fx18 - LD ST, Vx Fx1E - ADD I, Vx Fx29 - LD F, Vx Fx33 - LD B, Vx Fx55 - LD [I], Vx Fx65 - LD Vx, [I]

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SLIDE 4

Chip-8 Hardware Specifications

  • 64x32 bit display
  • 64B stack
  • 4KB memory
  • 16-key input
  • 16B register file
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SLIDE 5

Keyboard Layout

▪O – Reset ▪P – Pause ▪Enter – Start ▪Keyboard Mapping

1 2 3 4 Q W E R A S D F Z X C V 1 2 3 C 4 5 6 D 7 8 9 E A B F

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SLIDE 6

2

Emulator Layout

About as nice looking as this powerpoint

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SLIDE 7

Linux to SoCKit Bridge

Chip-8

Framebuffer

4K Memory

V2 V3 V4 V5 V6 V7 VA VB VC VD VE VF V0 V1 V8 V9 I

Sound Timer Delay Timer

PC SP

Stack 64B

16 Key Keyboard CPU

Font set (80B)

Linux

Read/Write State

1-bit Sound Channel VGA Out Keyboard out

Note: Identical to our design in

  • ur proposal
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SLIDE 8

Chip8 Driver

Linux Layout

Chip8 Executable Keyboard

Keyboard Listener Status Printer

  • Some Instructions required an

iowrite then an ioread

File Reader

.ch8 file

Fontset Instruction Verification Chip8 Read/Write ioread/ iowrite

To FPGA

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SLIDE 9

Chip8_Top

Hardware Layout

1-bit Sound Channel VGA Out

Register File Stack Memory Framebuffer

Buffer Memory

CPU BCD RNG ALU Arbitrator (always_ff loop) Sound Timer Delay Timer

Note: This is not a bus, all modules have their own channels

From Linux

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SLIDE 10

3

Module Design

Insert something snarky here

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SLIDE 11

Chip8-Top as Master Control Unit

If chipselect Parse address

If Stage == If Stage == 1

If state == Chip8_RUNNING

If 50000 > Stage >= 2

If Stage >= 50000 Update values if write

Note: Stage is incremented on each clock cycle while state == Chip8_Running and the device is not waiting for keyboard input

Do nothing Load PC into memaddr

Load Instruction

Operate on

  • utput

from CPU Update values in memory

No No No No No

Set stage =

Yes Yes Yes Yes Yes Yes

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SLIDE 12

Framebuffer Double Buffer

Buffer Framebuffer Arbitrator

  • The Framebuffer manages two 64x32 bit memories in

an effort to reduce flicker

  • The arbitrator will copy the buffer over to the

framebuffer only when it has been 4 CPU cycles since the last draw instruction or if it has been 10 CPU cycles since the last copy

  • Chip8 erases sprites by drawing them over existing

pixels which can cause extreme flickering

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SLIDE 13

Draw Instruction Over Multiple Cycles

reg_addr1 = instruction[11:8]; reg_addr2 = instruction[ 7:4]; num_rows_written = {7'b0,stageminus16[31:7]}; mem_addr1 = num_rows_written + reg_I_readdata; mem_request = 1'b1; fb_addr_x = reg_readdata1 + ({5'b0, stageminus16[6:4]}); fb_addr_y = reg_readdata2 + ({4'b0, num_rows_written[3:0]}); fb_writedata = mem_readdata1[3'h7 - stageminus16[6:4]] ^ fb_readdata; fb_WE = (num_rows_written < {28'h0, instruction[3:0]}) & (&(stage[3:0])); bit_overwritten = (mem_readdata1[3'h7 - stageminus16[6:4]]) & (fb_readdata) & fb_WE; isDrawing = 1'b1;

  • The locations being drawn are a function of the

stage

  • We need to make sure the memory has enough time

to propagate, which means that we are looking at the [6:4] bits of stage for x, and [10:7] for y

  • 16 <= stage <= 272
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SLIDE 14

Draw Instruction Over Multiple Cycles

Stage:

11 10 9 8 7 6 5 4 3 2 1 Number of rows written X offset WE …

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SLIDE 15

4

Testbenches Galore

Aggressively tested

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SLIDE 16

Testbenched Modules

  • CPU
  • Stack
  • ALU
  • Memory
  • Framebuffer
  • Top level
  • Random number

generator

  • BCD
  • Register file
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SLIDE 17

5

Project Workflow

Our tips to surviving all nighters in 1235 Mudd

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SLIDE 18

Timeline

▪We lagged behind goals during the semester, but we completed the final goal.

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SLIDE 19

Challenges

▪Memory was not always as ready as we were ▪Installing Linux on an FPGA is more difficult than bathing cats ▪Bugs are very common and FPGAs do not have proper pesticides yet

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SLIDE 20

Lessons Learned

▪Write testbenches early ▪Test givens (including megafunctions, especially megafunctions)

▪Start early! ▪During testing, bugs are your best friend

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SLIDE 21

Demo Time!

Hope you like Paddles and Tapeworms