SLIDE 1 Athens University
Paris Sphicas Vassilis Karageorgos (Diploma)
NCSR Demokritos
Theo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer) Katerina Zachariadou
Global Trigger Processor Emulator
SLIDE 2 RTP TPG FES LV1 TTC FED GTP TTS FRL RCN RU EVM BCN BDN GTP
L V 1 A
BackPressure BackPressure
BU Global Trigger Processor
Timing, Trigger & Control
SLIDE 3
- Generate Level-1 triggers (according to trigger rules).
- Sent triggers to TimingTriggerControl system
- Generate Event Number, BX counts and Trigger record
data to be sent to the Event Manager (via S-Link64)
- Receive Trigger Throttling System levels (Ready, Busy, Error)
Global Trigger Emulator Tasks: TTC GTP TTS EVM
SLIDE 4
Global Trigger Processor Running on PC#1 Event Manager Running on PC#2 Trigger Throttling System Running on PC#3 Intercommunication between programs via sockets over TCP/IP Vassilis Karageorgos University of Athens Diploma work
GTP-EVM-TTS simulation
SLIDE 5 Hardware components (final)
Quartus + DK1: FPGA code
TTC-ex
TTC-vi
VME
FEDs
PCIbus
GTP emulation G3
PCI-MXI2-VME L V 1 A c c
EVM emulation G3 S-LINK64 TTS
PCIbus
PC#2: Linux OS
PIII 512MB,550MHz
PC#1:Linux OS Control VME Control G3 PC#3: Wind. 2000
1GB, 2.6GHz
SLIDE 6 GENERIC-III , S-LIN64
A
D E B C F
- A. FPGA (APEX –Altera 200K usable logic gates)
- B. 32 MB SDRAM (133Mhz)
- C. 1 MB Flash
- D. S_Link64 connectors (data transmission)
- E. User connectors
- F. PCI interface for 32b/64b @33/66MHz
S-LINK64
SLIDE 7 S-LIN64
Data link to connect front-end to readout at any stage in a dataflow environment Data movement,error detection, return channel for flow control CMC transmitter card: Converts S-LINK64 signals to LVDS format CMC receiver card: Converts LVDS signals to S-LINK64 signals On-board FIFO(32Kbytes) buffers incoming data
SLIDE 8 FEDs
PCIbus
GTP emulation G3
PCI-MXI2-VME LV1Acc
EVM emulation S-LINK64 TTS
PCIbus
TTC-ex
TTC-vi
VME Hardware components (Actual)
PC#1: Linux OS Labview 6.1/RUlib Control PCI bus Control G3
Quartus + DK1: FPGA code
G3
HP54615B
For hardware tests
LV1Acc
PC#2:
Linux OS
PC#3: Wind. 2000
PIV 250MB, 800MHZ
SLIDE 9 VHDL, AHDL
Quartus 2.2-Altera software
PCI control SLINK-64 control SDRAM control
GTP emulation GTP emulator schematic
DK1.1 Celoxica design software In Handel-C
PCI bus
PC Parallel port with a byte-blaster OS: WindowsXX OS: Linux
SLIDE 10 PCI Controller:
- PCI communication (Dominique Gigi-CERN)
- Registers for Control, Status, Error, Reset operations (Isidoros Michailakis)
PCI control
SLIDE 11 GTP Local FIFO
MEM_FULL S-LINK64
(Back_Pressure)
MEM_FULL
S-LINK64 CONTROL S-LINK64 DATA[63..0] PCI control
GTP- transmitter
DATA[63..0]
WRITE_MEM
Command GTP
SLIDE 12
DATA[63..0]
EVM-receiver
S-LINK64 CONTROL PCI control Command
Local FIFO
S-LINK64 DATA[63..0]
SLIDE 13 S-LINK64 Controller (by Isidoros) Read local fifo Transfer data
S-LINK64 control
BackPressure PCI
transmitter
SLIDE 14
Lemo Output
BX_gen BX Bx_Rndm LV1A
bxn evn Write_evm
GTP_to_EVM_data (evn[31:12]+bxn[11:0]) FIFO_full (Backpressure)
S-LINK64 BackPressure
GTP- part Local FIFO
DATA[63..0]
SLIDE 15 DK1 module that generates the LHC proton beam structure (40.8MHz) 3564 bunches = {[(72b +8e)x3+30e]x2+[(72b+8e)x4+31e]}x3 + {[(72b+8e)x3+30e]x3+81e} Clock = 80 MHz (for tests used the PCI clock @33MHz )
- BX is created as in LHC
- LV1Acc occurs only on full bunches
BX generator module
Simulator output:
SLIDE 16
Lemo Output
BX_gen BX Bx_Rndm LV1A
bxn evn Write_evm
GTP_to_EVM_data (evn[31:12]+bxn[11:0]) FIFO_full (Backpressure)
S-LINK64 BackPressure
Local FIFO
DATA[63..0]
BX_Rndm module
SLIDE 17
- Random number generator (22 bits long Period = 4x106 events)
- At non empty BXs generates LV1Accept signals randomly
at a frequency of 100KHz (or at any frequency [4Hz, 100KHz])
- Associates a BX Number [0,3563] and an Event Number
BX_rndm module
BX_rndm module tasks:
SLIDE 18
DK1 Handel-C code Edif file Symbol for BX_rndm in Quartus
CLK BX
BXN EVN
BX_rndm module
LV1-A rate
LV1A
SLIDE 19
For this test LV1A @ 50KHz
LV1A on the scope
SLIDE 20
Lemo Output
BX_gen BX Bx_Rndm LV1A
bxn evn Write_Evm
GTP_to_EVM_data (evn[31:12]+bxn[11:0]) FIFO_full (Backpressure)
S-LINK64 BackPressure
Local FIFO
DATA[63..0]
Write_Evm module
SLIDE 21
- 1. Prepares data to be sent to the local FIFO
- 2. Checks the FIFO full flag (BackPressure)
- 3. Writes data in FIFO if not full.
If the local FIFO is full the data are lost. BX number FIFO full event number
Write_Evm module
WEN DATA[63..0]
SLIDE 22
Write_Evm module timing
SLIDE 23
Local FIFO Lemo Output
BX_gen BX Bx_Rndm LV1A
bxn evn Write_evm
GTP_to_EVM_data (evn[31:12]+bxn[11:0]) FIFO_full (Backpressure)
S-LINK64 BackPressure
Local FIFO
DATA[63..0]
SLIDE 24
Local FIFO
LOCAL FIFO (by Isidoros) FIFO : 1024 x 64 bits words, rw MUX for accessing the Control, Status etc registers
SLIDE 25
Receiver vi running on PC#2:
Get data
GTP EVM via SLINK-64 tests GTP vi running on PC#1:
Generate Level1 Accept triggers at user defined frequency Send data to the Event Manager
SLIDE 26 GTP emulator conceptual design LHC beam structure, LV1A signal , EVN, BXN SLINK-64 control GTP EVM via SLINK-64
Summary
EVM
Quartus + DK1: FPGA code
GTP
LV1A
Control G3+VME
SLINK-64
TTC GTP TTS EVM
SLIDE 27 Ready Busy inhibit
- Synchr. failure inhibit + synchr command via TTC to FED’s
(reset counters) Overflow reduction of trigger rate
Future Plans
set of Trigger Rules : “No more than N Level-1 Triggers in a given time interval”.
TTS signals
TTC
GTP
LV1A TTS
EVM
FED
BackPressure
Further tests of the design+integration tests
- f all components in a complete GTP emulator :
- BackPressure signals from TTS & EVM
- Generate Level-1 triggers
according to trigger rules
- Implement Trigger Summary Block
- Standard (FEDkit) receiver
SLIDE 28
SLIDE 29
RECEIVER
GTP emulator
SLINK
Byteblaster to the scope
G3
