The ATLAS Level-1 Central Trigger Processor Core Module (CTP_CORE) - - PowerPoint PPT Presentation

R.Spiwoks IEEE NSS2004, Rome, 19/10/2004 1 of 21

The ATLAS Level-1 Central Trigger Processor Core Module (CTP_CORE)

• Introduction
• Central Trigger Processor (CTP)
• Core Module (CTP_CORE)
• Testbeam Results

On behalf of

• P. Borrego Amaral1, N. Ellis1, P. Farthouat1, P. Gallno1, J. Haller1
• H. Pessoa Lima Jr.2, T. Maeno1, T. Pauly1, I. Resurreccion Arcas1,
• J. M. de Seixas2, G. Schuler1, R. Spiwoks1, R. Torga Teixeira1, T. Wengler1

1CERN, 2Universidade Federal de Rio de Janeiro

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The ATLAS Experiment

General-purpose Experiment at CERN’s Large Hadron Collider (LHC): Proton-Proton collisions at 14 TeV centre-of-mass energy. About 25 collisions per bunch crossing (BC) every 25 ns (40 MHz)

• ⇒ Interaction rate of 1 GHz.

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The Trigger/DAQ System

75 kHz 2 kHz 200 Hz Rate 2.5 µs 10 ms 2 s Level-1 Trigger: Electronics + Firmware Level-2 Trigger + Event Filter: Computers + Networks Available Time + Software

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The Level-1 Trigger System

See Poster N33-103 on the ATLAS Level-1 Central Trigger System. See Poster N33-104 on the ATLAS Local Trigger Processor.

Preprocessor Cluster Processor Jet/Energy Processor Barrel Trigger End-cap Trigger

Central Trigger Processor

calo muon

(e/γ & τ/h) (jet & energy) (RPC) (TGC)

Muon-CTP-Interface

detector front-end

LTP TTC BUSY

TTC Partition

LTP TTC BUSY

TTC Partition

LTP = Local Trigger Processor TTC = Timing, Trigger and Control ATLAS has ~ 40 TTC Partitions TGC = Thin-gap Chambers RPC = Resistive Plate Chambers BUSY = Tree of ROD_BUSY Modules

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The Central Trigger Processor (1)

• Trigger Input:
• Multiplicities from Calorimeter and Muon Triggers:

electrons/photons, taus/hadrons, jets, and muons;

• Energy flags from Calorimeter Trigger:

ΣET , ET

miss , ΣET jet

• Calibration requests from sub-detectors.
• Other specialized triggers: scintillators, beam pick-ups, etc.

⇒ Up to a total number of 160 trigger inputs at any one time. Plus internal triggers from CTP core module: random triggers, prescaled clock, bunch crossing groups.

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The Central Trigger Processor (2)

• Level-1 Accept (L1A)
• Derived from trigger inputs according to trigger menu:
• Up to 256 trigger items are made from combinations of

conditions on the trigger inputs, e.g.

1EM10 ≡ at least one electron/photon with ET ≥ 10 GeV 1MU6 ≡ at least one muon with pT ≥ 10 GeV/c XE20 ≡ missing energy of at least 20 GeV

• Each trigger item has a mask, a priority1 and a prescaling factor.

1 for dead-time (see later, CTP Core Module)

• L1A is the OR of all trigger items.
• An example of a trigger menu might contain

1MU6 mask = ON, priority = LOW, prescaling = 1000 2MU6 mask = ON, priority = HIGH, prescaling = 1 1EM20 AND XE20 mask = ON, priority = LOW, prescaling = 1 ...

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The Central Trigger Processor (3)

• Additional Functionality:
• Trigger type word (8 bits) accompanying every L1A.
• Dead-time in order to prevent front-end buffers becoming full

(see later, CTP Core Module).

• Region-of-Interest (RoI) for the Level-2 Trigger and

event data for the Read-out System (ROS) and for monitoring.

• Timing signals, e.g Event Counter Reset (ECR), ...
• Constraints:
• Trigger latency target, i.e. from trigger input to L1A:

100 ns ≡ 4 BC.

• Trigger menu changes with physics/beam/detector conditions.

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CTP - The Design

CTP_MI (Machine Interface) Timing CTP_IN (Input Module) Trigger input CTP_MON (Monitoring Module) Bunch-to-bunch monitoring CTP_CORE (Core Module) Trigger menu + Readout CTP_OUT (Output Module) Trigger fan-out CTP_CAL (Calibration Module) Sub-detector calibration requests

M I I N I N I N M O N C O R O U T O U T O U T E VMEbus COM bus (common) PIT bus (pattern-in-time) CAL bus (calibration requests)

BC/ORBIT 4 × SDP[30..0] L2_Link/RO_Link 5 × LTP Link 4 × SDP[30..0] 4 × SDP[30..0]

C A L

CAL[30..0] 5 × LTP Link 5 × LTP Link

O U T

5 × LTP Link TST/beam pick-up

9U VME64x + custom backplanes

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CTP - The Trigger Path

CTP_IN modules receive, synchronize and align the trigger inputs, and route them to the PIT bus (Pattern-in-time). CTP_CORE module receives and synchronizes the PITs, compares with trigger menu and generates Level-1 Accept (L1A), sends L1A to the COM bus. CTP_OUT receives L1A from the COM bus and fans it out to sub-detector LTPs.

M I I N I N I N M O N C O R O U T O U T O U T E COM bus (common) PIT bus (pattern-in-time) C A L O U T trigger input L1A

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CTP - The Timing Path

CTP_MI module receives timing signals from LHC, generates additional timing signals and sends all to the COM bus. CTP_OUT modules receive busy signals from sub-detector LTPs and send them to the COM bus. All CTP modules receive timing signals from the COM bus.

M I I N I N I N M O N C O R O U T O U T O U T E COM bus (common) C A L O U T BCK, ORBIT from LHC busy from sub-detectors

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CTP - The Readout & Monitoring

CTP_CORE module sends Region-of-Interest (RoI) information to the Level-2 Trigger and event data to the Readout System. CTP_MON produces a bunch-by-bunch histogram of signals from the PIT bus. All CTP modules provide monitoring data to the VMEbus.

M I I N I N I N M O N C O R O U T O U T O U T E VME bus C A L O U T Region-of-Interest information to Level-2 event data to Readout System

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CTP - The Calibration Requests

CTP_OUT modules receive calibration requests from sub-detector LTPs and send them to the CAL bus. CTP_CAL time-multiplexes calibration requests, receives additional trigger inputs and sends all to a CTP_IN module.

M I I N I N I N M O N C O R O U T O U T O U T E CAL bus (calibration requests) C A L O U T calibration requests from Sub-detectors additional trigger inputs

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The CTP Core Module (1)

• Trigger Combinations:

Combinations of signals from the PIT bus + internal to CTP_CORE using Look-up Tables (LUT) for trigger conditions, and Content-addressable Memories (CAM) for combinations of trigger conditions. Each CAM contains a 256-bit word and is ternary, i.e. allows bitwise matching of “0”, “1” or “don’t care”. Implemented using Xilinx Virtex II Pro (XC2VP50).

LUT LUT LUT CAM CAM CAM 160 PIT 256 Trigger Conditions 256 Trigger Items + 12 internal

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The CTP Core Module (2)

• Prescaling and Masking:
• Prescale: programmable 24-bit down-counter

⇒ 256 TAP (Trigger items after Prescaling).

• Mask: programmable mask + dead-time + busy

⇒ 256 TAV (Trigger items after Veto).

• OR: over all 256 TAVs

⇒ 1 L1A (Level-1 Accept).

• Generate 8-bit trigger type using eight 256-bit masks.

Implemented using Altera Stratix (EP1S60).

256 Trigger Items 256 TAP 256 TAV L1A busy dead-time OR Trigger Type

trigger type mask trigger type mask trigger type mask

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The CTP Core Module (3)

• Dead-time:

Simple deadtime:

• Constant time after each L1A:

No L1As for n BCs after each L1A. Current baseline (programmable): n = 4. Complex deadtime:

• Leaky-bucket algorithm:

Not more than n L1As in m BCs. Current baseline (programmable): 8 L1As in 80 µs. ⇒ Two leaky-bucket algorithms are used, associated to the priority of each trigger item (high/low). Implemented using same FPGA as for Prescaling and Masking.

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The CTP Core Module (4)

• Readout & Monitoring:

Copied into FIFOs at every L1A:

• 160 Signals from the PIT bus + 12 internal triggers;
• 256 Trigger items before prescaling (TBP);
• 256 Trigger items after prescaling (TAP);
• 256 Trigger items after veto (TAV);
• 64-bit UTC time-stamp (linked to GPS) with 5-ns jitter.

Implemented in two Altera Stratix (EP1S60) with 128 signals for data exchange between them (firmware to be written):

160 PIT 256 TBV 256 TAP 256 TAV L1A UTC 128 S-Link S-Link Level-2 Trigger Readout System VMEbus FPGA1 FPGA2

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The ATLAS Combined Testbeam

Test beam programme during 2004 for prototypes and final modules

• f all ATLAS sub-detectors and trigger and data acquisition.

beam

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The Level-1 Trigger at the Combined Testbeam

Trigger Input: Calorimeter Trigger: 4×3 bit e/γ + 4×3 bit jet multiplicities +1 bit total ET, Muon Trigger: 6×3 bit muon multiplicities, Scintillators: 3×1 bit scintillators. CTP: 1 CTP_MI, 1 CTP_IN (out of up to 3), 1 CTP_CORE, 1 CTP_OUT (out of up to 4), 1 CTP_MON.

Muon Trigger Barrel: RPC Sector Logic Muon Trigger End-cap: TGC Sector Logic Calorimeter Trigger Common Merger Modules Muon-CTP-Interface Central Trigger Processor (MUCTPI) (CTP) Scintillators

M I I N M O N C O R E O U T

LTP

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The CTP at the Combined Testbeam

CTP_MI CTP_IN CTP_CORE CTP_MON CTP_OUT

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CTP - Some Results

• Trigger Generation:

51 signals from PIT bus used to form 18 trigger items. Prescaling and masking tested to work correctly. L1A used as trigger for readout of the combined sub-detectors.

• Latency Measurement (preliminary!):

Scintillator Trigger → L1A at CTP_CORE ≈ 130 ns. But some cable delays not taken into account and CTP timing not yet optimised. Scintillator Trigger L1A at CTP_CORE L1A at LTP

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Conclusion

CTP_CORE has been used during testbeam to generate trigger using 51 trigger inputs and 18 trigger items. CTP latency is already close to the target of 100 ns. Work on the CTP will continue in laboratory, e.g. CTP_CORE readout and corrections to firmware which were identified during the testbeam. CTP will be available for ATLAS commissioning next year.