RD53A Emulator and 64b/66b Serial Link Status Lev Kurilenko - - PowerPoint PPT Presentation

RD53A Emulator and 64b/66b Serial Link Status

Lev Kurilenko (levkur@uw.edu)

University of Washington

LBL Instrumentation Progress Meeting June 16 2017

1

Emulator Block Diagram

2

• Emulator fully implemented,

except Tx block

• Rx being co-developed for DAQ

systems

• DAQ and RD53 Emulators

implemented on two KC705 FPGA boards

• Capable of sending 64 bits

unencoded hit data

Clock Data Recovery

• TTC data received w/o accompanying

clock

• Clock can be recovered using data
• Prior knowledge of data clock

required

• Data oversampled at 4x the incoming

data rate

• A[0] = 0, A[1] = 1, phase A sees rising

edge

• C[0] = 1, C[1] = 0, phase C sees falling

edge

• Phases A, B, C, D range from 0 to 270
• Best phase selected

Oversampling Phase Selection

Source: Yangming Ke, Undergraduate at UW

3

DAQ

• DAQ implemented on FPGA
• Initialized in ‘Lock’ state,
• Guarantees transmission will not

begin until Emulator and DAQ are synced

• Commands generated via LFSR
• UART communication

– 'o' = oneshot trigger (single trigger) – 'c' = continuous trigger – 's' = stop continuous trigger – 'd' = data command (chosen at random from LFSR; full command will complete with one 'd')

• ‘TTC Out’ sent to RD53 Emulator

4

• Standard I/O protocol

– Used in 10 Gigabit ethernet

• Scrambles incoming 64 bit words

– DC balance – 4-bit Hamming distance

• Appends 2-bit sync header

– Data block (01) – Control block (10) – (11), (00) illegal – Guarantees transition every 66 bits

64b/66b Aurora

5

Current Implementation - 64b/66b

• Motivation is to provide Aurora

core not dependant on Xilinx specific IP

• Components (tested and working)

– Encoder – 64b/66b Scrambler – 64b/66b Gearbox – SerDes

• In development

– Block Sync – Channel Bonding – Clock Compensation

Source: Aurora 64B/66B Protocol Specification (Xilinx)

6

Testing and Debug

• ModelSim, Xilinx ILA (Integrated Logic Analyzer)
• Testing and Debug branch created containing ILAs

– Allows for targeted testing via triggers – Incremental Compilation – May use VIO (Virtual Input/Output) in the future

7

Aurora 64b/66b Testing

8

Current Work

• Develop and test the Aurora 64b/66b Rx/Tx blocks
• Fix bugs as they come up (e.g. Global Pulse generation)
• Improve debugging capabilities
• Cater emulator to interface with YARR DAQ
• Collaborate with Timon and Nikola on YARR

9

Collaborators

• Joe Mayer began work on the emulator (graduated)

– Thesis available: https://cds.cern.ch/record/2198312?ln=en

• Logan Adams (graduated)
• Lev Kurilenko - Graduate student
• Dustin Werran – Graduate student
• Douglas Smith – Undergraduate student
• Yangming Ke – Undergraduate student
• Advised by

– Shih-Chieh Hsu (UW Physics) – Scott Hauck (UW EE) – FPGA professor

10

Questions?

11