C55 intro Highlights of the new C55x DSP Architecture The C55x DSP - - PowerPoint PPT Presentation

C55 intro

Highlights of the new C55x™ DSP Architecture

 The C55x DSP core supports new programming capabilities,

while maintaining complete software compatibility with existing C54x code

 Advanced Automatic Power Management

the C55x DSP core continually monitors which parts of the chip are in use, powering them off when they are not needed the C55x DSP core continually monitors which parts of the chip are in use, powering them off when they are not needed

 Increased Idle Domains

The C55x DSP core extends the three fixed idle choice of the C54x with a total of 64 user configurable combinations of the following six components: CPU, Cache, Peripherals, DMA, Clock generator, External Memory Interface

 Additional Hardware

Dual 17 x 17-bit MACs, a second 16-bit ALU, four new data registers (which can be used for simple computations) and four 40-bit accumulators

 Increased parallelism

Additional Buses and Expanded Addressing - To make sure that throughput can attain the theoretical maximum made possible by the new computational hardware, the C55x DSP core features:

• Three 16-bit data read buses
• Two 16-bit data write buses
• One 32-bit program bus
• Six 24-bit address buses

C5000 Peripheral Features

 USB 2.0 Full-Speed  Hardware UART  Inter Integrated-Circuit (IIC)  Analog-to-Digital Converter (ADC)  Multimedia Card / Secure Digital (MMC/SD)  Video Hardware Extensions  Multi-Channel Buffered Serial Ports (McBSPs)  Direct Memory Access (DMA)  8/16-bit Enhanced Host Port Interface (EHPI)

 Hardware UART (UART) - C5404, C5407, C5502

Industry standard asynchonous communication that performs serial-to-parallel conversions on data received from a peripheral device or the CPU.

 Inter Integrated-Circuit (IIC) - C5502, C5509

Provides glueless serial interface between C55x DSPs and IIC-compatible devices. Transmit/Received up to 8-bit data to/from the C55x DSP through the 2-wire IIC interface.

 Analog-to-Digital Converter (ADC) - C5509

• Up to 10-bit successive-approximation analog-to-digital

architecture achieves very low power consumption.

• Maximum sampling rate of 21.5 kHz.
• Suitable for sampling analog signals such as

monitoring the voltage drop across a potentiometer on a user interface panel or sample the voltage on a battery monitoring circuit.

 Video Hardware Extensions - C5510, C5509

Three hardware extensions carefully tailored for the C55x DSP generation include:

• Discrete Cosine Transform (DCT)/ Inverse DCT
• Pixel Interpolation
• Motion Estimation

Delivers exceptional video codec performance freeing up more than half the CPU bandwidth to handle additional functions such as color space conversion, user-interface functions, TCP/IP, and voice-processing.

 Multi-Channel Buffered Serial Ports (McBSPs)

High-speed full-duplex serial ports:

 Full-Duplex communication

Direct interface to

 C5000 devices  Codecs  T1/E1 framers  MVIP switching compatible devices  ST-BUS compliant devices  IOM-2 compliant devices  AC97 compliant devices  IIS compliant devices  SPI™ devices

On-chip companding (COMpress & exPAND) hardware for data compression/expansion in either µ-law or A-law format

 Direct Memory Access (DMA)

• Transfers data between points in the memory space

without CPU intervention

• Allows data movements to/from internal memory,

external memory and peripherals to occur in background

• f CPU operation
• Operates independent of CPU

 8/16-bit Enhanced Host Port Interface (EHPI)

• Parallel port for host processor to directly access DSP's

memory space

• Configure DSP memory access for either Host Only

Mode (HOM) or Shared Access Mode (SAM)

• Host & DSP can exchange information via

internal/external memory

• Access to entire DSP internal memory (access to a

portion of DSP external memory via the internal DMA bus)