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- Chap. 18
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DSP Applications
DSP applications are often real time but with a wide variety of sample rates
- High rates
– Radar – Video
- Medium rates
– Audio – Speech
- Low rates
Chapter 18: Programmable DSPs Keshab K. Parhi and Viktor Owall DSP - - PowerPoint PPT Presentation
Chapter 18: Programmable DSPs Keshab K. Parhi and Viktor Owall DSP - - PowerPoint PPT Presentation
Chapter 18: Programmable DSPs Keshab K. Parhi and Viktor Owall DSP Applications DSP applications are often real time but with a wide variety of sample rates High rates Radar Video Medium rates Audio Speech Low rates
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...with different demands on
- numeric representation
– float or fixed – and nmber of bits
- Throughput/speed
- Power/energy dissipation
- Cost
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- Chap. 18
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DSP features
D D D
x(n) h0 h3 h2 h1 y(n)
Fast Multiply/Accumulate (MAC)
- FIR
- FFT
- etc.
- Multiple Access Memories
- Specialized addressing modes
- Specialized execution control (loops)
- Specialized interfaces, e.g. AD/DA
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- Chap. 18
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Addressing Modes
- Implied addressing
P=X*Y;
- peration sets location
- Immediate data
AX0=1234
- Memory direct
R1=Mem[101]
- Register direct
sub R1, R2
- Register indirect
A0=A0+ *R5
- Register indirect with increment/decrement
A0=A0+ *R5++ A0=A0+ *R5--
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Standard DSP Alternatives
PCs or Workstations
- Non-real time
- low requirements
General purpose microprocessors
- slower for DSP applications
- might be one µproc. there anyway
Custom
- perfomance
- low cost at volume
- High development cost
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- Chap. 18
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Standard Processors vs. Special Purpose
Algorithm Special Purpose Standard Processor
Processor Cores Domain Specific Processors etc.
- Programmable
- Low Design cost
- Standard Interface
- Good supply of tools
- High Calculation Capacity
- Low Power
- User defined Interface
- Variable Wordlength
- Low Price at Volume
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- Chap. 18
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Main MEM
Conflicting req.
- Throughput
- Flexibility
- Power Consumption
- Time to market
Processor Core
ASIC ASIC
Main MEM
Dist. MEM
Local busses and Distributed memory to decrease data transfers MIPS intensive algorithms in dedicated HW to increase throughput and save power Flexibility by using programmable processor core
Architectural Partitioning
Processor Core
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- Chap. 18
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Fixed point DSP
Motorola DSP56000x
X0 X1 Y0 Y1 Shifter ALU A (56) B (56) Shifter/ Limiter 24 24 24 24 24 24 24 24 56 56 56 56 56 Operand Registers Accumulators
- Usually DSP has single cycle
multiplier, may be pipelined
- Double wordlength out
+ guard bits
- scaling
- Altenative is mult
with reduced wordlength output, e.g. 24
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Memory Structures, von Neuman
Addresss bus Data bus
Processor Core Memory
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Memory Structures, Harvard
Addresss bus 2 Data bus 2
Processor Core Memory A
Addresss bus 2 Data bus 2
Memory B Original Harvard
- one data
- one program
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TI Processors, high speed
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TI Processors, low power
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TI, C64
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TI, C55
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Processor Architectures
SIMD – Single Instruction Multiple Data
Program Processor Processor Processor Processor
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Processor Architectures
MIMD – Multiple Instruction Multiple Data
Processor Processor Processor Processor Program Program Program Program
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Processor Architectures
VLIW – Very Long Instruction Words
Functional Unit
VLIW Instruction Control Unit
Functional Unit Functional Unit Functional Unit
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Split Processors
Functional units can be split into submodules, e.g. for images (8bits) TI320C80, 1 RISC 4 x 32bit DSP which can be split into 8bit modules
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Vector Processors
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- Chap. 18
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Low Power MMAC
Multiplier Multiple Accumulator
- V. Sundararajan and K.K. Parhi, "A
Novel Multiply Multiple Accumulator Component for Low Power PDSP Design", Proc. of 2000 IEEE Int. Conf.
- n Acoustics, Speech and Signal
Processing, Vol. 6, pp. 3247-3250, Istanbul, June 2000
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