Programmable Data Plane at Terabit Speeds Milad Sharif SOFTWARE - - PowerPoint PPT Presentation

SOFTWARE ENGINEER

Programmable Data Plane at Terabit Speeds

Milad Sharif

AUGUST 2018

PISA: Protocol Independent Switch Architecture

PISA − Block Diagram

3

Match+Action Stage

Memory ALU

Programmable Parser Programmable Match-Action Pipeline

PISA − Match-Action Unit

• Multiple simultaneous lookups and actions can be supported

Sequential Execution (Match dependency)

Memory ALU Memory ALU Memory ALU Memory ALU

Staggered Execution (Action dependency)

Memory ALU Memory ALU

Parallel Execution (No dependency)

Introducing Tofino

Four Match+Action Pipelines

• Fully programmable PISA Embodiment
• Single Shared Packet Buffer
• 16nm technology

Port Configurations

• 260 × 25 SerDes, support 1G, 10G, 25G, 40G, 50G, and 100G ports

CPU Interfaces

• PCIe: Gen3 ×4/ ×2/ ×1
• Dedicated 100GE port

6.5Tb/s TofinoTM− Overview

6

Match+Action Pipeline 2 Match+Action Pipeline 3 Match+Action Pipeline 1 Match+Action Pipeline 0 Shared Packet Buffer + TM MAC + Serial I/O

Tofino − Simplified Block Diagram

7 pipe 0 Rx MACs

10/25/40/50/100

Ingress Pipeline Tx MAC

10/25/40/50/100 Control & configuration

Reset / Clocks PCIe CPU MAC DMA engines pipe 1 Rx MACs

10/25/40/50/100

Ingress Pipeline Tx MAC

10/25/40/50/100

pipe 2 Rx MACs

10/25/40/50/100

Ingress Pipeline Tx MAC

10/25/40/50/100

pipe 3 Rx MACs

10/25/40/50/100

Ingress Pipeline Tx MAC

10/25/40/50/100

Traffic Manager Egress Pipeline Egress Pipeline Egress Pipeline Egress Pipeline

Fully-Programmable Parser

8

Eth. IPv4 IPv6 UDP TCP

Protocol== 0x11 Protocol== 0x06

From MAC TCAM SRAM shift control Match Field selection Next state Next state

Input Shift Register Match Field Extract

Data State

Output Field Extractor

Action

Packet Header Vector

• A set of uniform containers that carry the headers and metadata.

along the pipeline

• Fields can be packed into any container or their combination.
• Packing is decided by PHV Allocation pass in the compiler.

Packet Header Vector (PHV)

9

8-bit words

8 8

16-bit words

16 16 32 32

32-bit words

Match−Action Unit

Match RAM/TCAM

Key

×

Xbar

#

Action RAM ALUs: Meters, Statistisc, Stateful Delay Instr. RAM

Instruction Address Operand Data

PHV

Match−Action Pipeline

Match Action Unit

Parser

Full packet Match Action Unit Match Action Unit Match Action Unit

Deparser

Match−Action Pipeline

Parser

Full packet

uRPF IPv4 IPv6 ACL Deparser

ACL IPv4 IPv6

• Multiple small tables per stage
• Large tables spread over multiple stages

Unified Match−Action Pipeline

MAU 0 PHV MAU n PHV Combined Ingress/Egress Match-Action Pipeline

Ingress Parser

Ingress Packet body

Queues And Packet Buffers

Ingress Deparser

Ingress Packet Constructor

Ingress Buffer

Unified Match−Action Pipeline

MAU 0 PHV MAU n PHV

Combined Ingress/Egress Match-Action Pipeline

Ingress Packet body Egress Packet body Egress header

Queues And Packet Buffers Ingress Buffer

Ingress Deparser

Ingress Packet Constructor

Egress Deparser

Egress Packet Constructor

Ingress Parser Egress Deparser

Unified Match−Action Pipeline

Recirculation Buffer (Packet Reference, Metadata)

MAU 0 PHV MAU n PHV

Combined Ingress/Egress Match-Action Pipeline

Ingress Packet body Egress Packet body Egress header

Queues And Packet Buffers Ingress Buffer

Ingress Deparser

Ingress Packet Constructor

Egress Deparser

Egress Packet Constructor

Ingress Parser Egress Deparser

Programming Tofino

Tofino Architecture

• Data plane interfaces
• Intrinsic Metadata

ingress_mac_tstamp − ingress timestamp assigned by MAC ucast_egress_port − output port

• Tofino-specific Extern

Registers, Counters, Meters, Filters, etc.

/// Register extern Register<T, I> { /// Instantiate an array of <size> registers. /// The initial value is undefined. Register(bit<32> size); /// Initialize an array of <size> registers and set /// their value to initial_value. Register(bit<32> size, T initial_value); /// Return the value of register at specified index. T read(in I index); /// Write value to register at specified index. void write(in I index, in T value); }

Runtime Configuration

Extern Libraries Arch. Definition P416 Core Library Target-Specific Configuration BF-Runtime info

Backend

Fronend

P4 Compiler

Application BF-Runtime APIs V1Model

Provided by Barefoot Networks

ASIC driver PSA

P4 Architecture Model User Defined

Packet Test Framework P4 Visualization P4 Program ASIC Model

/// Indexed counter with `size’ independent /// counter values. extern Counter<W, I> { /// Constructor /// @type_param W : width of the counter value. /// @type_param I : width of the counter index. /// @param type : counter type. Packet an byte /// counters are supported. Counter(bit<32> size, CounterType_t type); /// Increment the counter value. /// @param index: index of the counter to be /// incremented. void count(in I index); }

Multi−Pipeline configuration

Extern Libraries Arch. Definition P416 Core Library App1.p4

P4 Compiler

App2.p4

P4 Compiler Pipeline Configuration Pipeline Configuration

MSHARIF@BAREFOOTNETWORKS.COM

Thank You

Contact Information