200 MS/s ADC implemented in a FPGA employing TDCs Harald Homulle | Francesco Regazzoni | Edoardo Charbon 15 April 2015 1 ATDC
Contents Developing FPGA ADCs • Introduction • System Architecture • Results • Conclusion 2 ATDC
1. INTRODUCTION 3 ATDC
FPGA ADCs? 2.5 255 Amplitude [V] Digital code 0 0 Time [ns] Time [ns] 4 ATDC
Applications Sensor networks Industrial control systems Physics experiments Medical electronics 5 ATDC
TDC Implementation • Carrychain (delayline) TDC • Propagating carry • Dedicated carry routing • Smallest delay available: ∼ 21 ps • Thermometer time stamp 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 C arry4 C arry4 C arry4 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 + + + + + + + + + + + + carry ¡out carry ¡out carry ¡out carry ¡in carry ¡in carry ¡in 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 6 ATDC
TDC Limitations Clock domain crossing • Carrychain (delayline) TDC • Performance limitations: • Bubbles • Ultra wide bins • Causes: • Carry look ahead • Clock • Domains (each 16 slices) Large space crossing • Slew / Slack • Setup / Hold time violations • Large space (each 16 slices) • Inter slice delay vs. Intra slice delay Carry4 slice 7 ATDC
in(14 ) in(14 ) in(13 ) in(13 ) Thermometer decoder in(12 ) in(12 ) in(11 ) in(11 ) in(10 ) in(10 ) & Bubbles in(9) in(9) in(8) in(8) in(7) in(7) out(4) out(4) • Bubble interpretation in(6) in(6) • 0010111 à 4 • 0010111 à 3 in(5) in(5) • 0011111 à 5 in(4) in(4) • Bubble is consistent w.r.t. time out(2) out(2) • No correction in(3) in(3) • Counter on last 16 bits in(2) in(2) out(1) count ¡ones out(1) in(1) in(1) out(0) out(0) in(0) in(0) 8 ATDC
Dithering ultra wide bins • Dithering equalizes bin delay with a pseudo random non linear mapping on equally spaced bins • Increase in systems linearity at expense of random noise Bin 0 28 29 30 31 32 N Bin 0 28 29 30 31 32 N Bin 0 28 29 30 31 32 N Delay Delay Delay Mapping probability Dithered Dithered output output 9 ATDC
2. SYSTEM ARCHITECTURE 10 ATDC
FPGA ADC Working Principle 2.5 ¡ns C LK ¡/ S TOP V OUT V R EF V I N S TAR T Positive edge timing Negative edge timing measured with TDC 1 measured with TDC 2 11 ATDC
Reference ramp C L K ¡ 200 ¡MHz F P G A V OUT DC M S T O P R R E F TDC ¡1 C INT D OUT US B3 S T A R T V R E F R ead-‑out LVDS S T A R T TDC ¡2 V IN S T O P 12 ATDC
System & TDCs • 2 carrychains TDC • 200 MHz C arry4 • 128 adders + + + + • 32 slices C arry4 • Total slices V R EF LVD S < 400 S TAR T + + + + V I N • P = 410 mW S TOP D FF C LK 200 ¡MHz Therm om eter ¡decoder Read-‑out C LK 100 ¡MHz US B3 13 ATDC
3. RESULTS 14 ATDC
Transfer curve Resolution (LSB) = 17 mV 0 – 2.5 V 7.2 bit Before calibration After calibration 15 ATDC
DC measurement (single shot) 4 3 x 10 One shot histogram Gaussian fit 2.5 2 Counts jitter 1.5 σ < 2 LSB 1 0.5 0 140 150 160 170 180 190 200 ATDC code 16 ATDC
Non linearities – DNL/INL • DNL [-0.9 1.3] LSB • INL [-0.5 1.1] LSB 1.5 1.5 DNL INL 1 1 Non Linearity [LSB] Non Linearity [LSB] 0.5 0.5 0 0 -0.5 -0.5 -1 -1 50 100 150 200 250 50 100 150 200 250 ATDC code ATDC code 17 ATDC
AC measurement – Time Domain 1 V 1 µ s 18 ATDC
AC measurement – Frequency Domain 2 10 1 ¡MH z ¡S ine ¡W a ve 1 ¡MH z ¡S ine ¡W a ve 2 10 SNDR = 28 dB SNDR ¡= ¡28 ¡dB SNDR = 37 dB SNDR ¡= ¡37 ¡dB Ma g nitude ¡[dB ] Ma g nitude ¡[dB ] 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 F re que ncy ¡[MH z ] F re que ncy ¡[MH z ] Before calibration After calibration 19 ATDC
Comparison with other FPGA ADCs Carrychain Clock phase Delta Sigma XADC TDC TDC [7] Modulator [5,6] [10] Clock speed [MHz] 200 360 100 Conversion speed 200 22.5 0.5 to 0.05 1 [MS/s] Voltage range [V] 0 – 2.5 0 – 3.3 0 – 3.3 0 – 1.0 Digital range 7.2 bit 6 bit 10 bit to 16 bit 12 bit ENOB 6 bit 9 bit 10 bit Resolution [mV] 17 52 3 0.25 DNL [LSB] [-0.9 1.3] ± 1 INL [LSB] [-0.5 1.1] ± 2 Error σ [LSB] 2 1 External 1 4 2 - 3 0 components 20 ATDC
Comparison with ASIC – Murmann survey Conversion energy vs. SNDR 1.E+07 1.E+06 1.E+05 1.E+04 P/f snyq [pJ] This work 1.E+03 ISSCC 2010-2014 1.E+02 ISSCC 2005-2009 1.E+01 ISSCC 1997-2004 1.E+00 VLSI 2010-2014 1.E-01 10 20 30 40 50 60 70 80 90 100 110 120 SNDR @ f in,hf [dB] 21 ATDC
Comparison with ASIC – Murmann survey Signal frequency vs. SNDR 1.E+11 This work ISSCC 2010-2014 1.E+10 ISSCC 2005-2009 ISSCC 1997-2004 1.E+09 VLSI 2010-2014 VLSI 2005-2009 1.E+08 VLSI 1997-2004 f in,hf [Hz] Jitter=1psrms 1.E+07 Jitter=0.1psrms 1.E+06 1.E+05 1.E+04 1.E+03 10 20 30 40 50 60 70 80 90 100 110 120 SNDR @ f in,hf [dB] 22 ATDC
4. CONCLUSION 23 ATDC
Conclusion • Best performing FPGA ADC implemented with 200 MS/s, 6 bits of ENOB and a high linearity. • 10 × higher sampling rate with 1 bit higher resolution (compared to clock phase TDC based ADC) • 200 × higher sampling rate with 4 bits lower resolution (compared to Xilinx XADC: found in Xilinx 7 series FPGAs) • FPGA ADC can compete with somewhat older ASIC ADCs • Next steps: • 1 GS/s ADC • Auto calibration • Multichannel • DAC 24 ATDC
VHDL Source – Available online 25 ATDC
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