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ATDC
200 MS/s ADC implemented in a FPGA employing TDCs
Harald Homulle | Francesco Regazzoni | Edoardo Charbon
15 April 2015
2
ATDC
Contents
Developing FPGA ADCs
- Introduction
- System Architecture
- Results
- Conclusion
200 MS/s ADC implemented in a FPGA employing TDCs Harald Homulle | - - PowerPoint PPT Presentation
200 MS/s ADC implemented in a FPGA employing TDCs Harald Homulle | - - PowerPoint PPT Presentation
200 MS/s ADC implemented in a FPGA employing TDCs Harald Homulle | Francesco Regazzoni | Edoardo Charbon 15 April 2015 1 ATDC Contents Developing FPGA ADCs Introduction System Architecture Results Conclusion 2 ATDC 1.
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ATDC
- 1. INTRODUCTION
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ATDC
FPGA ADCs?
Digital code Time [ns]
255
Amplitude [V] Time [ns]
2.5
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ATDC
Applications
Sensor networks Industrial control systems Physics experiments Medical electronics
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TDC Implementation
- Carrychain (delayline) TDC
- Propagating carry
- Dedicated carry routing
- Smallest delay available: ∼21 ps
- Thermometer time stamp
1 carry ¡in 1 1 1 1 1 1 1 1
+ + + +
C arry4 1 1 carry ¡out carry ¡in 1 1 1 1 1 1 1 1
+ + + +
C arry4 carry ¡out 1 carry ¡in 1 1 1 1 1 1 1 1
+ + + +
C arry4 1 carry ¡out
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TDC Limitations
- Carrychain (delayline) TDC
- Performance limitations:
- Bubbles
- Ultra wide bins
- Causes:
- Carry look ahead
- Clock
- Domains (each 16 slices)
- Slew / Slack
- Setup / Hold time violations
- Large space (each 16 slices)
- Inter slice delay vs. Intra slice delay
Carry4 slice Large space crossing Clock domain crossing
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Thermometer decoder & Bubbles
- Bubble interpretation
- 0010111 à 4
- 0010111 à 3
- 0011111 à 5
- Bubble is consistent w.r.t. time
- No correction
- Counter on last 16 bits
in(0) in(1) in(2) in(3) in(4) in(5) in(6) in(7) in(8) in(9) in(10 ) in(11 ) in(12 ) in(13 ) in(14 )
- ut(0)
- ut(1)
- ut(2)
- ut(4)
in(0) in(1) in(2) in(3) in(4) in(5) in(6) in(7) in(8) in(9) in(10 ) in(11 ) in(12 ) in(13 ) in(14 )
- ut(0)
- ut(1)
- ut(2)
- ut(4)
count ¡ones
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ATDC
Dithering ultra wide bins
- Dithering equalizes bin delay with a pseudo random non linear
mapping on equally spaced bins
- Increase in systems linearity at expense of random noise
Bin 0 28 29 30 31 32 N Delay Dithered
- utput
Bin 0 28 29 30 31 32 N Delay Dithered
- utput
Mapping probability Bin 0 28 29 30 31 32 N Delay
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ATDC
- 2. SYSTEM ARCHITECTURE
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ATDC
C LK ¡/ S TOP S TAR T V R EF V I N V OUT
2.5 ¡ns
FPGA ADC Working Principle
Positive edge timing measured with TDC 1 Negative edge timing measured with TDC 2
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ATDC
LVDS
DC M V IN R R E F C INT V R E F TDC ¡1 F P G A
S T A R T S T O P
TDC ¡2
S T A R T S T O P
V OUT C L K ¡200 ¡MHz R ead-‑out US B3 D OUT
Reference ramp
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ATDC
LVD S
+ + + + + + + +
D FF Therm om eter ¡decoder Read-‑out
V R EF V I N C LK
200 ¡MHz
C LK
100 ¡MHz
US B3
C arry4 C arry4
S TAR T S TOP
- 2 carrychains TDC
- 200 MHz
- 128 adders
- 32 slices
- Total slices
< 400
- P = 410 mW
System & TDCs
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ATDC
- 3. RESULTS
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ATDC
Transfer curve
After calibration Before calibration
Resolution (LSB) = 17 mV
7.2 bit 0 – 2.5 V
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ATDC
140 150 160 170 180 190 200 0.5 1 1.5 2 2.5 3 x 10
4
ATDC code Counts One shot histogram Gaussian fit
DC measurement (single shot)
jitter σ < 2 LSB
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ATDC
Non linearities – DNL/INL
- DNL
[-0.9 1.3] LSB
- INL [-0.5 1.1] LSB
50 100 150 200 250
- 1
- 0.5
0.5 1 1.5 ATDC code Non Linearity [LSB] INL 50 100 150 200 250
- 1
- 0.5
0.5 1 1.5 ATDC code Non Linearity [LSB] DNL
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ATDC
AC measurement – Time Domain
1 V 1 µs
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1 2 3 4 5 6 7 8 9 10 10
2
F re que ncy ¡[MH z ] Ma g nitude ¡[dB ] 1 ¡MH z ¡S ine ¡W a ve SNDR ¡= ¡37 ¡dB
AC measurement – Frequency Domain
1 2 3 4 5 6 7 8 9 10 10
2
F re que ncy ¡[MH z ] Ma g nitude ¡[dB ] 1 ¡MH z ¡S ine ¡W a ve SNDR ¡= ¡28 ¡dB
After calibration Before calibration SNDR = 28 dB SNDR = 37 dB
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Comparison with other FPGA ADCs
Carrychain TDC Clock phase TDC [7] Delta Sigma Modulator [5,6] XADC [10] Clock speed [MHz] 200 360 100 Conversion speed [MS/s] 200 22.5 0.5 to 0.05 1 Voltage range [V] 0 – 2.5 0 – 3.3 0 – 3.3 0 – 1.0 Digital range 7.2 bit 6 bit 10 bit to 16 bit 12 bit ENOB 6 bit 9 bit 10 bit Resolution [mV] 17 52 3 0.25 DNL [LSB] [-0.9 1.3] ± 1 INL [LSB] [-0.5 1.1] ± 2 Error σ [LSB] 2 1 External components 1 4 2 - 3
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1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 10 20 30 40 50 60 70 80 90 100 110 120
P/fsnyq [pJ] SNDR @ fin,hf [dB]
This work ISSCC 2010-2014 ISSCC 2005-2009 ISSCC 1997-2004 VLSI 2010-2014
Comparison with ASIC – Murmann survey Conversion energy vs. SNDR
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1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 10 20 30 40 50 60 70 80 90 100 110 120 fin,hf [Hz]
SNDR @ fin,hf [dB]
This work ISSCC 2010-2014 ISSCC 2005-2009 ISSCC 1997-2004 VLSI 2010-2014 VLSI 2005-2009 VLSI 1997-2004 Jitter=1psrms Jitter=0.1psrms
Comparison with ASIC – Murmann survey Signal frequency vs. SNDR
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- 4. CONCLUSION
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- Best performing FPGA ADC implemented with 200 MS/s, 6
bits of ENOB and a high linearity.
- 10×higher sampling rate with 1 bit higher resolution
(compared to clock phase TDC based ADC)
- 200×higher sampling rate with 4 bits lower resolution
(compared to Xilinx XADC: found in Xilinx 7 series FPGAs)
- FPGA ADC can compete with somewhat older ASIC ADCs
- Next steps:
- 1 GS/s ADC
- Auto calibration
- Multichannel
- DAC
Conclusion
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