Zynq nq Evaluatio tion and nd Devel elopmen ent Board Cris - PowerPoint PPT Presentation

Zynq nq Evaluatio tion and nd Devel elopmen ent Board Cris istia ian Sisterna na Universidad Nacional de San Juan Argentina ZedBoard ICTP 1

Zed edBoard Main Compon onents 2 ZedBoard ICTP

Zed edBoard Main Connec ector ors to b be e Used 3 ZedBoard ICTP

Conec ection on Bet etwee een P PC-Zed edBoa oard 4 ZedBoard ICTP

Prog ogramming the Zed edBoard 5 ZedBoard ICTP

DRA DRAM Me Memory o 512 Mbytes DDR3 connected to the PS part of the Zynq o The DDR3 is controled by the DRAM Controller o It is posible to add more memory to the PL part using the Memory Interface Generator (MIG), for example using a daughter card connected to the FMC connector. o PS DDR Bandwidth o By default the DDR Controller clock is 533MHz o Total Bw: 4 * 533 * 2 = 4.2 GB/s o PL DDR Bandwith …. ?? 6 ZedBoard ICTP

256 Mbit- Serial NOR PMOD Flash PMOD LPC FMC 68 Single Ended 10/100/1000 34 Differential Connector Ethernet Phy LEDs (8) USB OTG Push Buttons(5) User I/O DIP Switch(8) SD Card AUDIO USB-UART LD9 (PS) HDMI Buttons (PS) VGA 512MB (32 bits)533MHz OLED Processor Done Blue LED Subsystem Reset Program Push Button Analog Mixed Signaling Clock (AMS) Connector USB-JTAG PL Clock Source 100MHz 7 ZedBoard ICTP

ZedBoard Hardware User Guide Zynq Architecture ICTP - MALAYSIA 2016 8

9 Zynq Architecture ICTP - MALAYSIA 2016

ZedBoa oard Cl Clock ck Sourc rces 10 Zynq Architecture ICTP - MALAYSIA 2016

ZedBoa oard Available I/O O fo for the User (1) 1) 11 Zynq Architecture ICTP - MALAYSIA 2016

ZedBoa oard Available I/O O fo for the User (2) 2) 12 Zynq Architecture ICTP - MALAYSIA 2016

ZedBoa oard Available I/O O fo for the User (3) 3) 13 Zynq Architecture ICTP - MALAYSIA 2016

ZedBoard P PMOD OD Connec ector ors 14 Zynq Architecture ICTP - MALAYSIA 2016