Zynq nq Evaluatio tion and nd Devel elopmen ent Board Cris - - PowerPoint PPT Presentation

▶

Feb 18, 2023 105 likes •259 views

Zynq nq Evaluatio tion and nd Devel elopmen ent Board Cris istia ian Sisterna na Universidad Nacional de San Juan Argentina ZedBoard ICTP 1 Zed edBoard Main Compon onents 2 ZedBoard ICTP Zed edBoard Main Connec ector ors to

SLIDE 1

Zynq nq Evaluatio tion and nd Devel elopmen ent Board

ZedBoard ICTP

Cris istia ian Sisterna na Universidad Nacional de San Juan Argentina

SLIDE 2

ZedBoard ICTP

Zed edBoard Main Compon

nents

SLIDE 3

ZedBoard ICTP

Zed edBoard Main Connec ector

rs to b

be e Used

SLIDE 4

ZedBoard ICTP

Conec ection

n Bet

etwee een P PC-Zed edBoa

SLIDE 5

ZedBoard ICTP

Prog

gramming the Zed

edBoard

SLIDE 6

512 Mbytes DDR3 connected to the PS part of the Zynq
The DDR3 is controled by the DRAM Controller
It is posible to add more memory to the PL part using the Memory

Interface Generator (MIG), for example using a daughter card connected to the FMC connector.

PS DDR Bandwidth
By default the DDR Controller clock is 533MHz
Total Bw: 4 * 533 * 2 = 4.2 GB/s
PL DDR Bandwith …. ??

ZedBoard ICTP

DRA DRAM Me Memory

SLIDE 7

ZedBoard ICTP

512MB (32 bits)533MHz 256 Mbit- Serial NOR Flash SD Card USB OTG USB-UART USB-JTAG HDMI VGA AUDIO OLED PL Clock Source 100MHz Clock Processor Subsystem Reset User I/O

LEDs (8) Push Buttons(5) DIP Switch(8)

10/100/1000 Ethernet Phy LPC FMC Connector

68 Single Ended 34 Differential

PMOD PMOD Analog Mixed Signaling (AMS) Connector Done Blue LED Program Push Button LD9 (PS) Buttons (PS)

SLIDE 8