UC UC b Overview Leader Election Protocol Dynamic Voltage - - PowerPoint PPT Presentation

UC UC b

APPLICATIONS

UC UCb

Overview

Leader Election Protocol Dynamic Voltage Scaling Optimal Reconfiguration

• f FPGA

Memory Interface

UC UC b

Leader Election Protocol

UC UCb

Leader Election

2 3 1 Protocol by Leslie Lamport

UC UCb

Leader Election

2 3 1 (3,0) (0,0) (2,0) (1,0) (leader,hops)

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Timeout

2 3 1 (3,0) (0,0) (2,0) (1,0)

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Flooding

2 3 1 (3,0) (0,0) (2,0) (1,0) (1,2,1,0)

(1,0,1,0)

(1,3,1,0) (src,dst,leader,hops)

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Flooding

2 3 1 (3,0) (0,0) (2,0) (1,0) (1,2,1,0)

(1,0,1,0)

(1,3,1,0)

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Flooding

2 3 1 (1,1) (0,0) (2,0) (1,0) (1,2,1,0)

(1,0,1,0)

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Forwarding

2 3 1 (1,1) (0,0) (2,0) (1,0) (1,2,1,0)

(1,0,1,0)

(3,2,1,1)

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Forwarding

2 3 1 (1,1) (0,0) (2,0) (1,0) (1,2,1,0)

(1,0,1,0)

(3,2,1,1)

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Forwarding

2 3 1 (1,1) (0,0) (1,1) (1,0) (3,2,1,1) (2,3,1,1)

(2,0,1,1)

(1,0,1,0)

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Leader Election

2 3 1 (1,1) (0,0) (1,1) (1,0)

UC UCb

Leader Election

2 3 1 (1,1) (0,0) (1,1) (1,0)

UC UCb

Leader Election

2 3 1 (0,2) (0,0) (0,1) (0,1)

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Variable timeout

time timeout hops 1 2 timer

U p d a t e r e c e i v e d U p d a t e r e c e i v e d U p d a t e r e c e i v e d

T i m e

• u

t T i m e

• u

t

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Leader Election Claim to be verified

Correct leader is known at a node i after t(i) = ΔTO + ΔTDELAY + di·ΔMDELAY

A model checking problem

IMP ² ▫>t(i) l(i)=L(i) for all i.

UC UCb

Modelling (RT) protocols

Protocol stacks Users Medium

All, Thanks for the spec. It seems to run fine. As expected, it's 2 or 3 orders of magnitude faster than TLC. I'm wondering if your algorithms could be used for checking specs written in a higher level language like TLA+. All, Thanks for the spec. It seems to run fine. As expected, it's 2 or 3 orders of magnitude faster than TLC. I'm wondering if your algorithms could be used for checking specs written in a higher level language like TLA+.

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Modelling (RT) protocols

Protocol stacks Users

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Modelling (RT) protocols

Protocol stacks Users Messages

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Modelling the election protocol

2 1

Per process disti: N leaderi: Node timeouti: N Message src: Node dst: Node leader: Node hopss: N

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Global Declaration

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Message

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Node[id]

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Local Declarations (Node[id])

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Optimisations

Reducing the number of active variables

If variable is never used until next reset, then the value does not matter.

Symmetry of message processes

The message processes are symmetric: It does not matter which is used to transfer a message.

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Dynamic Voltage Scaling

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Performance vs Ressource-Efficiency ?

• Consumer constantly

demand better functionality, flexibility, availability, …

• .. increase in resources

needed:

• Time
• Energy
• Memory
• Bandwidth
• ..
• Application of CUPPAAL to

modeling, analysis and synthesis of resource- efficient schedules for real- time systems.

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Power Management

Dynam ic Voltage Scaling

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Energy in Processor

• Power consumption mainly by dynamic power
• Supply voltage reduction => decreased frequency

1 > α

α

; V ~ f

1)

• (

dd clk

2 dd L . clk 2 dd L dynamic

V C E f V C P ⋅ = ⋅ ⋅ =

cycle pr dynamic energy Vdd delay

Vdd

We may miss deadlines

A non-experts understanding of CMOS

UC UCb

Task Scheduling

T2 is running { T4 , T1 , T3 } ready

• rdered according to some

given priority: (e.g. Fixed Priority, Earliest Deadline,..)

T1 T1 T2 T2 Tn Tn

Scheduler Scheduler

2

1 4 3 ready done stop run P(i), [E(i), L(i)], .. : period or earliest/ latest arrival or .. for Ti C(i): execution time for Ti D(i): deadline for Ti

utilization of CPU

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Modeling Task

T1 T1 T2 T2 Tn Tn

Scheduler Scheduler

2

1 4 3

ready done stop run

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Modeling Scheduler

T1 T1 T2 T2 Tn Tn

Scheduler Scheduler

2

1 4 3

ready done stop run

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Modeling Queue

T1 T1 T2 T2 Tn Tn

Scheduler Scheduler

2

1 4 3

ready done stop run

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Schedulability = Safety Property

A฀ ¬(Task0.Error or Task1.Error or …)

¬(Task0.Error or Task1.Error or …)

May be extended with preemption

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Energy Optimal Scheduling

“Choose” Scaling/ Cost (Freq/ Voltage) Using Priced Timed Automata C T1 T1 T2 T2 Tn Tn

Scheduler Scheduler

2

1 4 3

ready done stop run

F:= ?? ; V:= ??

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Energy Optimal Scheduling =

c1 c2 c3 cn t1 t2 t3 tn

σ

Value of path σ: val(σ) = limn→∞ cn/tn Optimal Schedule σ* : val(σ* ) = infσ val(σ)

Accumulated cost Accumulated time

¬(Task0.Error or Task1.Error or …)

Optim al I nfinite Path

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Energy Optimal Scheduling =

c1 c2 c3 cn t1 t2 t3 tn

σ

Value of path σ: val(σ) = limn→∞ cn/tn Optimal Schedule σ* : val(σ* ) = infσ val(σ)

Accumulated cost Accumulated time

¬(Task0.Error or Task1.Error or …)

THEOREM: σ* is computable THEOREM: σ* is computable

Bouyer, Brinksma, Larsen ´03

Optim al I nfinite Path

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Approximate Optimal Schedule

E[] (not (Task0.Error or Task1.Error or Task2.Error) and (cost> = M imply time > = N)) = E[] φ(M ,N)

σ ² [] φ(M,N) imply val(σ)· M/ N

C= M C= M C= M

T> = N T< N X

X X

Optimal infinite schedule modulo cost-horizon C= M

T< N T< N T> = N

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Preliminary Results

EDF w preemption no DVS: avr.: 48

P1=D1=32 C1=6 P2=D2=48 C2=18 P3=D3=64 C3=12

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Preliminary Results

EDF w preemption w DVS: avr.: 43.37

Cost horizon: 2,000

P1=D1=32 C1=6 P2=D2=48 C2=18 P3=D3=64 C3=12

Optimal Reconfiguration of FPGA

Utilizing new features of UPPAAL 4 .0 User-defined functions Types & Select Due to Jacob I. Rasmussen

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Field Programmable Gate Array

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The Problem

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The Problem

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Example

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Example

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Example

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Example

1

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Example

1

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UPPAAL Model

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UPPAAL Model

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UPPAAL Model

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UPPAAL Model

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Memory Interface

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Memory Management

Advanced Noise Advanced Noise Reduction Techniques Reduction Techniques

e1,2 e0,5 e0,4 e0,3 e0,2 e2,4 e2,3 e2,2 e1,5 e1,4 e1,3 e3,2 e3,4 e3,3 e3,5 e2,5

S w e e p I n t e g r a t i

• n

Airport Surveillance Costal Surveillance

echo 9.170 GHz 9.438 GHz

Combiner (VP3)

Frequency Diversity

combiner

Radar Video Processing Subsystem

UC UCb

Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

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Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

A single buffer

UC UCb

Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

Clock

broadcast chan tick; const CYCLE 10; // 100MHz = 10ns cycle

UC UCb

Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

const REGSIZE 64; // 64 byte = 512 bits int[-4,1028] buffer; int[0,64] register

Input Buffer Input Register

UC UCb

Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

Memory (-ies)

const REFRESH_PERIOD 15525; const REFRESH_TIME 100;

UC UCb

Adder 1

S = A + S' - A'

Adder 2

T = B + T' - B'

Buffer 1

1 Kbytes

Buffer 2

1 Kbytes

Buffer 9

2 Kbytes

Buffer 8

2 Kbytes

Buffer 7

2 Kbytes

Buffer 6

512 bytes

Buffer 4

2 Kbytes

Buffer 3

512 bytes

Input A 8 (100MHz) A' S' 16 (100 MHz) Input B 8 (100 MHz) T' B' T S Output S Output T 256 (100 MHz) 128 (200 MHz) SDRAM Buffer 5

512 bytes

B 8 (100MHz) 8 (100MHz) 8 (100MHz) 16 (100 MHz) 16 (100 MHz) 16 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz) 256 (100 MHz)

Arbiter

Arbiter (round robin)