UC UC b Overview Leader Election Protocol Dynamic Voltage - PowerPoint PPT Presentation

APPLICATIONS UC UC b

Overview � Leader Election Protocol � Dynamic Voltage Scaling � Optimal Reconfiguration of FPGA � Memory Interface UC UCb

Leader Election Protocol UC UC b

Leader Election 2 1 0 3 Protocol by Leslie Lamport UC UCb

Leader Election (leader,hops) (2,0) (1,0) 2 1 (0,0) 0 3 (3,0) UC UCb

Timeout (2,0) (1,0) 2 1 (0,0) 0 3 (3,0) UC UCb

Flooding (2,0) (1,0) (1,2,1,0) 2 1 (0,0) (1,0,1,0) 0 (1,3,1,0) 3 (3,0) (src,dst,leader,hops) UC UCb

Flooding (2,0) (1,0) (1,2,1,0) 2 1 (0,0) (1,0,1,0) 0 (1,3,1,0) 3 (3,0) UC UCb

Flooding (2,0) (1,0) (1,2,1,0) 2 1 (0,0) (1,0,1,0) 0 3 (1,1) UC UCb

Forwarding (2,0) (1,0) (1,2,1,0) 2 1 (0,0) (1,0,1,0) 0 (3,2,1,1) 3 (1,1) UC UCb

Forwarding (2,0) (1,0) (1,2,1,0) 2 1 (0,0) (1,0,1,0) 0 (3,2,1,1) 3 (1,1) UC UCb

Forwarding (1,1) (1,0) 2 1 (0,0) (2,0,1,1) (1,0,1,0) 0 (2,3,1,1) (3,2,1,1) 3 (1,1) UC UCb

Leader Election (1,1) (1,0) 2 1 (0,0) 0 3 (1,1) UC UCb

Leader Election (1,1) (1,0) 2 1 (0,0) 0 3 (1,1) UC UCb

Leader Election (0,1) (0,1) 2 1 (0,0) 0 3 (0,2) UC UCb

Variable timeout hops timeout timer 2 1 0 U U U T T time p p p i i m m d d d a a a e e t t t o o e e e u u r r r t t e e e c c c e e e i i i v v v e e e d d d UCb UC

Leader Election Claim to be verified Correct leader is known at a node i after t(i) = Δ TO + Δ TDELAY + d i ·Δ MDELAY A model checking problem IMP ² ▫ > t(i) l(i)=L(i) for all i. UC UCb

Modelling (RT) protocols Users All, All, Protocol stacks Thanks for the spec. Thanks for the spec. It seems to run fine. It seems to run fine. As expected, it's 2 or As expected, it's 2 or 3 orders of magnitude 3 orders of magnitude Medium faster than TLC. I'm faster than TLC. I'm wondering if your wondering if your algorithms could be algorithms could be used for checking used for checking specs written in a specs written in a higher level language higher level language like TLA+. like TLA+. UCb UC

Modelling (RT) protocols Users Protocol stacks UC UCb

Modelling (RT) protocols Users Protocol stacks Messages UC UCb

Modelling the election protocol 0 1 Per process dist i : N 2 leader i : Node timeout i : N Message src: Node dst: Node leader: Node hopss: N UC UCb

Global Declaration UC UCb

Message UC UCb

Node[id] UC UCb

Local Declarations (Node[id]) UC UCb

Optimisations � Reducing the number of active variables � If variable is never used until next reset, then the value does not matter. � Symmetry of message processes � The message processes are symmetric: It does not matter which is used to transfer a message. UC UCb

Dynamic Voltage Scaling UC UC b

Performance vs Ressource-Efficiency ? Consumer constantly � demand better functionality, flexibility, availability, … .. increase in resources � needed: Time � Energy � Memory � Bandwidth � .. � Application of CUPPAAL to � modeling, analysis and synthesis of resource- efficient schedules for real- time systems. UCb UC

Power Management Dynam ic Voltage Scaling UC UCb

Energy in Processor A non-experts understanding of CMOS Power consumption mainly by dynamic power � energy 2 P = C ⋅ V ⋅ f dynamic L dd clk 2 E = C ⋅ V . L dd dynamic pr cycle V dd Supply voltage reduction => decreased frequency � delay ( α - 1) f ~ V ; α > 1 clk dd We may miss deadlines V dd UCb UC

Task Scheduling utilization of CPU P(i), [E(i), L(i)], .. : period or earliest/ latest arrival or .. for T i C(i): execution time for T i D(i): deadline for T i T 1 T 1 ready Scheduler Scheduler done T 2 T 2 2 4 1 3 stop run T n T n { T 4 , T 1 , T 3 } ready T 2 is running ordered according to some given priority: UC UCb (e.g. Fixed Priority, Earliest Deadline,..)

Modeling Task ready T 1 T 1 Scheduler done Scheduler T 2 T 2 2 4 1 3 stop run T n T n UCb UC

Modeling Scheduler ready T 1 T 1 Scheduler done Scheduler T 2 T 2 2 4 1 3 stop run T n T n UCb UC

Modeling Queue ready T 1 T 1 Scheduler done Scheduler T 2 T 2 2 4 1 3 stop run T n T n UCb UC

Schedulability = Safety Property May be extended with preemption ¬ (Task0.Error or Task1.Error or …) A ฀ ¬ (Task0.Error or Task1.Error or …) UC UCb

Energy Optimal Scheduling Using Priced Timed Automata ready T 1 T 1 Scheduler done Scheduler T 2 T 2 4 1 3 2 stop run F:= ?? ; V:= ?? T n T n “Choose” Scaling/ Cost (Freq/ Voltage) C UCb UC

Energy Optimal Scheduling = Optim al I nfinite Path Accumulated cost c 3 c n c 1 c 2 t 3 t n σ t 1 t 2 Accumulated time ¬ (Task0.Error or Task1.Error or …) Value of path σ : val( σ ) = lim n →∞ c n /t n Optimal Schedule σ * : val( σ * ) = inf σ val( σ ) UCb UC

Energy Optimal Scheduling = Optim al I nfinite Path Accumulated cost c 3 c n c 1 c 2 t 3 t n σ t 1 t 2 Accumulated time ¬ (Task0.Error or Task1.Error or …) THEOREM: σ * is computable THEOREM: σ * is computable Bouyer, Brinksma, Larsen ´03 Value of path σ : val( σ ) = lim n →∞ c n /t n Optimal Schedule σ * : val( σ * ) = inf σ val( σ ) UCb UC

Approximate Optimal Schedule Optimal infinite schedule modulo cost-horizon T< N X T< N X T< N X T> = N T> = N C= M C= M C= M C= M E[] (not (Task0.Error or Task1.Error or Task2.Error) and (cost> = M imply time > = N)) = E[] φ (M , N) σ ² [] φ (M,N) imply val( σ ) · M/ N UCb UC

Preliminary Results EDF w preemption no DVS: avr.: 48 P 1 =D 1 =32 C 1 =6 P 2 =D 2 =48 C 2 =18 UC UCb P 3 =D 3 =64 C 3 =12

Preliminary Results Cost horizon: 2,000 EDF w preemption w DVS: avr.: 43.37 P 1 =D 1 =32 C 1 =6 P 2 =D 2 =48 C 2 =18 UC UCb P 3 =D 3 =64 C 3 =12

Optimal Reconfiguration of FPGA Utilizing new features of UPPAAL 4 .0 User-defined functions Types & Select Due to Jacob I. Rasmussen

Field Programmable Gate Array Informationsteknologi UC UCb

UCb UC Informationsteknologi The Problem

UCb UC Informationsteknologi The Problem

UCb UC Informationsteknologi Example

UCb UC Informationsteknologi Example

UCb UC Informationsteknologi Example

UCb UC Informationsteknologi Example 1

UCb UC Informationsteknologi Example 1

UCb UC Informationsteknologi UPPAAL Model

UCb UC Informationsteknologi UPPAAL Model

UCb UC Informationsteknologi UPPAAL Model

UCb UC Informationsteknologi UPPAAL Model

Memory Interface UC UC b

Memory Management Radar Video Processing Subsystem Frequency Diversity Advanced Noise Advanced Noise Reduction Techniques Reduction Techniques 9.170 GHz 9.438 GHz Costal Surveillance e 0,5 e 1,5 e 0,4 e 1,4 e 0,3 e 2,5 echo e 1,3 e 2,4 e 0,2 Combiner e 1,2 e 2,3 (VP3) e 2,2 e 3,5 e 3,4 e 3,3 e 3,2 combiner Airport Surveillance n o i t a r g e t n I p e e w S UCb UC

Input A Input B 8 (100MHz) 8 (100 MHz) Buffer 1 256 (100 MHz) 1 Kbytes Buffer 2 256 (100 MHz) 1 Kbytes Buffer 3 A' 8 (100MHz) 256 (100 MHz) 512 bytes Adder 1 Buffer 4 S' 16 (100 MHz) 256 (100 MHz) S = A + S' - A' 2 Kbytes 128 (200 MHz) Buffer 5 16 (100 MHz) 8 (100MHz) 256 (100 MHz) SDRAM 512 bytes Buffer 6 B' 8 (100MHz) 256 (100 MHz) B 512 bytes Adder 2 Buffer 7 T' 256 (100 MHz) T = B + T' - B' 16 (100 MHz) 2 Kbytes Buffer 8 T 256 (100 MHz) 16 (100 MHz) 2 Kbytes Buffer 9 S 256 (100 MHz) 2 Kbytes Output S Output T Arbiter UCb UC

Input A Input B 8 (100MHz) 8 (100 MHz) Buffer 1 256 (100 MHz) 1 Kbytes Buffer 2 256 (100 MHz) A single buffer 1 Kbytes Buffer 3 A' 8 (100MHz) 256 (100 MHz) 512 bytes Adder 1 Buffer 4 S' 16 (100 MHz) 256 (100 MHz) S = A + S' - A' 2 Kbytes 128 (200 MHz) Buffer 5 16 (100 MHz) 8 (100MHz) 256 (100 MHz) SDRAM 512 bytes Buffer 6 B' 8 (100MHz) 256 (100 MHz) B 512 bytes Adder 2 Buffer 7 T' 256 (100 MHz) T = B + T' - B' 16 (100 MHz) 2 Kbytes Buffer 8 T 256 (100 MHz) 16 (100 MHz) 2 Kbytes Buffer 9 S 256 (100 MHz) 2 Kbytes Output S Output T Arbiter UCb UC

Input A Input B 8 (100MHz) 8 (100 MHz) Buffer 1 256 (100 MHz) broadcast chan tick; 1 Kbytes const CYCLE 10; // 100MHz = 10ns cycle Buffer 2 256 (100 MHz) 1 Kbytes Buffer 3 A' 8 (100MHz) 256 (100 MHz) 512 bytes Adder 1 Buffer 4 S' 16 (100 MHz) 256 (100 MHz) S = A + S' - A' 2 Kbytes 128 (200 MHz) Buffer 5 16 (100 MHz) 8 (100MHz) 256 (100 MHz) SDRAM 512 bytes Clock Buffer 6 B' 8 (100MHz) 256 (100 MHz) B 512 bytes Adder 2 Buffer 7 T' 256 (100 MHz) T = B + T' - B' 16 (100 MHz) 2 Kbytes Buffer 8 T 256 (100 MHz) 16 (100 MHz) 2 Kbytes Buffer 9 S 256 (100 MHz) 2 Kbytes Output S Output T Arbiter UCb UC