Transistor Size Optimization Methodology for Logic Circuits - PowerPoint PPT Presentation

Transistor Size Optimization Methodology for Logic Circuits Considering Variations caused by BTI and Process TAU 2016 Thursday, March 10, 2016 Michitarou YABUUCHI, Kazutoshi KOBAYASHI Kyoto Institute of Technology 1

Kobayashi Lab. Summary Transistor Size Optimization Technique � BTI (Bias Temperature Instability) and process variations into consideration � Lifetime delay of logic path – 4.4% reduced � Area – no overhead � # of cells in library – 3x~ 2

Kobayashi Lab. Background – Aging Degradation + + A Y B Timing Delay Margin = Spec. Time ��������� �������������������������� ����������������������������� ������������� 3

� Kobayashi Lab. Transistor Size Optimization 9.3 Lp = Ln = 45 nm Delay RMS [ps] 9.2 Wp + Wn = 700 nm Wp 9.1 Wn 9.0 8.9 240/460 210/490 270/430 � ��� + � ��� Wn/Wp [nm] � ��� = 2 � Conventional – initial delay based 4

Kobayashi Lab. Impact of BTI on Inverter Slower to � dr increases by NBTI VDD turn ON (PMOS degradation) Input ＝１ Low High initial High Low aged Input ＝ 0 � df increase by PBTI VSS Slower to (NMOS degradation) turn ON � Since 45 nm process – Both BTI � Imbalance – � dr and � df degradation 5

Kobayashi Lab. Purpose of This Study Margin reduced Delay Efficient guardband Time � Propose – lifetime delay based � Key ideas – Consider “lifetime experience” in logic gate design – Optimize transistor size to reduce “BTIGinduced variation” � Design cells for DF (Duty Factor) = 0, 0.5, 1 6

� Kobayashi Lab. Sizing – BTIGInduced Variation Standard Normal Quantile � =10 8 s � ��� : cnst. �� =0.5 � =45 nm ⁄ � ��� ∝ 1 �� Vth shift [mV] � Enlarge transistor size – reduce BTI variation 7

Kobayashi Lab. Results of Size Optimization 11 DF=0.5 DF=0 Delay RMS [ps] Prop. 10 Larger PMOS DF=1 Larger NMOS 9 Conv. Initial 240/460 270/430 210/490 Wn/Wp [nm] Lp = Ln = 45 nm Wp + Wn = 700 nm 8

Kobayashi Lab. Simulation Result – INV Chain 4.4% Conventional (initial based) Initial: 64.8 ps Lifetime: 76.6 ps Proposed (lifetime based) Initial: 66.5 ps Lifetime: 73.2 ps initial Lifetime (1) Lifetime (0) � Lifetime delay – improved w/o area overhead 9

Kobayashi Lab. Conclusion � Transistor size optimization technique – Conventional – initial delay based – Lead to large timing margin – Proposed – lifetime delay based – Path delay of inverter chain – improved by 4.4% – No requirement of area overhead – Support dependable and efficient chip designs 10

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Kobayashi Lab. BTI (Bias Temperature Instability) Recoverable Component �� ∆� Permanent Component Time 0 Stress Relaxation NBTI (Negative BTI) on PMOS PBTI (Positive BTI) on NMOS � �� < 0 � �� > 0 65 nm~ 40 nm HKMG~ 12

Kobayashi Lab. Technique to Overcome Degradation Adaptive NonGadaptive Techniques Techniques Body biasing Sizing Adaptive Strengthen Supply Voltage � Overhead required � Based on aging prediction 13

Kobayashi Lab. Physics – Atomistic TrapGBased Model ATGB Model Gate Gate Dielectric Drain Source : Defect (capture) : Defect (emission) � Defect – capture and emit carriers 14

Kobayashi Lab. Calculate �� Distribution by BTI DefectGcentric distribution Input: transistor size, stress condition Product of Nt and η Nt: number of defect (Poisson dist.) η: impact of single defect (Exp. Dist.) Output: ∆� �� P. Weckx et al � , IRPS 2014 15

� Kobayashi Lab. Physics – Scaling of BTI Defect in gate dielectric Scaling Number of defect – decrease Impact of single defect – increase � Average � ��� – constant ⁄ � Deviation � ��� – area dependent ( ∝ 1 �� ) 16

Kobayashi Lab. AgingGaware Library Logic Simulation Tr. Size Optimization Signal Probability Profile AgingGaware Library Cells Gate Mapping 17

Kobayashi Lab. Optimization for MultiGinput Gate A=1 A=0 A=0 A=1 B=1 B=0 B=1 B=0 15 A=0, B=0 Delay RMS [ps] A=1, B=0 14 A=1, B=1 13 A=0, B=1 initial 12 320/380 290/410 260/440 Wn/Wp [nm] 18