INTRODUCTION TO CALD (Computer Aided Logic Design) Introduction - - PDF document

Department of Electrical and Computer Engineering

Slide 1

Robert Betz: 97

INTRODUCTION TO CALD (Computer Aided Logic Design) Introduction

• Late 1960’s-early 80’s – most logic design carried out using the TTL

(transistor transistor logic) or the CMOS (complementary metal oxide transistor) logic families. This design philosophy is now know as dis- crete logic design (although at the time of use it would not have been).

• 1980’s – growth of the PLA (Programmable Logic Array) and PAL

(Programmable Array Logic) chip technology. Allowed a number of product terms to be once only programmed into a single integrated

• circuit. Only implemented combinational circuits. See Figure 1 and

Figure 2.

• The next generation of the PLA/PAL technology allowed the circuits

to be programmed in the field and then erased and reprogrammed a number of times. Usually based on EPROM type technology for eras-

• ure. Flip flops also started to appear in on the outputs of some devices

allowing sequential circuits to be built. See Figure 3 and Figure 4.

• Late 1980’s – more sophisticated devices started to appear. These

were often known as EPLDs (Electrically Programmable Logic Devices) based on macrocell architectures, or FPGAs (Field Program- mable Gate Arrays) based on interconnected gates, or low level struc-

• tures. These devices contained many more flip flops and more

combinational logic capability compared to the earlier PLA/PAL type

• f circuitry.
• 1990’s – Devices now allow almost arbitrary logic to be implemented.

Very large devices, equivalent to 150,000 logic gates now available and the size of the devices is increasing.

Department of Electrical and Computer Engineering

Slide 2

Robert Betz: 97

PLA logic

• Used for combinational circuits

Function implemented below: F1=AB'+AC F2=AC+BC .

• Note that the PLA shown above is not typical – it is much too small

to be a practical PLA. More typical PLA may have 50 product terms, 10 inputs and 8 outputs.

• One must attempt to minimise the number of product terms so that

the limited number of AND gates are used.

• Has programmable AND and OR arrays in the device.

A B C F1 F2

Figure 1 : Typical PLA layout

Department of Electrical and Computer Engineering

Slide 3

Robert Betz: 97

PAL logic

• Used to implement combinational circuits
• Only has a programmable AND array – OR array is fixed. Easier to

program than the PLA but not a flexible.

1 2 3 4 5 6 7 8 9 10 AND gate inputs 1 2 3 4 5 6 7 8 9 Product terms F1 F2 F3 I1 I2 I3

Figure 2 : Classic PAL logic structure

10 input gates Fusible link points Buffer and inverter

Department of Electrical and Computer Engineering

Slide 4

Robert Betz: 97

Larger PLA/PAL logic families

• Now contain sequential elements.
• Example: Altera Classic EPLD series of devices – based on a mac-

rocell architecture .........

OE CLK

Output Enable/Clock Select Programmable Register Asynchronous Clear Pin, I/O & Macrocell Feedbacks Q Feedback Select To logic array Logic array Vcc Global Clock CLR

Figure 3 : Altera Classic Macrocell

D

Department of Electrical and Computer Engineering

Slide 5

Robert Betz: 97

Some notes

• Individual cells can be programmed for either combinational logic
• r sequential logic.
• Based on a PAL AND/OR array i.e. the AND array is programma-

ble.

• If an I/O pin is used as an input then it cannot be used as a macro-

cell output.

• Macrocell register can be programmed to be a D, T, JK, or SR flip

flop.

• Dedicated inputs are globally available to all macrocells.
• Feedback multiplexer may make the feedback signals available or

in the quadrant of the macrocell (depends on the particular part).

Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Global Bus Input Input Input Input Clk1 Clk2

Figure 4 : Internal block diagram of the Altera EP610 EPLD.

Department of Electrical and Computer Engineering

Slide 6

Robert Betz: 97

Enhanced Larger PLA/PAL Logic Family Devices

• These EPLDs are essentially an extension of the previous logic

family.

• Based on using logic array blocks (LABs) – a sort of super macro-

cell.

• Have more flexible interconnect structures.

I/O Control Block Macrocell Array Expander Product-Term Array LAB Interconnect PIA 24 16 4 to 16 I/O Pins per LAB 8 to 20 Dedicated Inputs to All Other LABs Feedback from I/O pins to LAB (Single-LAB devices only) PIA in Multi-LAB Devices Only LAB A

Figure 5 : Altera MAX 5000 Architecture

Department of Electrical and Computer Engineering

Slide 7

Robert Betz: 97

• The expanders are to complement the capabilities of the macrocell.

The expander product-term array consists of a group of unallocated, inverter product terms that can be used and shared by all the macro- cells in the LAB to create combinational and registered logic.

• All macrocell outputs are globally routed within a LAB using the

LAB interconnect.

• I/O control block consists of programmable tristate buffers and I/O

pins.

• The Programmable Interconnect Array (PIA) allows multiple LABs

to be connected together.

D Output Enable PRN Q CLRN Global Clock (one per LAB) To I/O control block Programmable register Array clock Clear Preset 8 or 20 Dedicated Inputs 24 programmable Interconnect signals (Multi-LAB devices) 32 or 64 Expander Product terms I/O feedback Macrocell feedback Logic Array

Figure 6 : Altera MAX 5000 Macrocell

Department of Electrical and Computer Engineering

Slide 8

Robert Betz: 97

8 or 20 Dedicated Inputs 24 Programmable Interconnect Signals (Multi-LAB devices) 32 or 64 Expander Product terms Macrocell feedbacks

Figure 7 : Expander product terms

to Macrocell Array

Department of Electrical and Computer Engineering

Slide 9

Robert Betz: 97

Modern Devices – Flex 8000

• Shall concentrate on the Flex 8000 series of devices as these will be

the devices used in the design project.

• The Flex 8000 (Flexible Logic Element Matrix) series differs from

the earlier Altera series of parts as it used SRAM based look-up tables (LUTs) to implement the logic functions, as opposed to the AND/OR structure inherited from PALs, as used in the earlier devices.

• Flex 8000 has up to 50,000 useable gates, 4,752 registers, and 360

I/O pins, depending on the variant of the chip chosen. Device to be used in the project is the EPF8820A which has 8,000 useable gates and 820 flip flops, 84 LABs, 672 logic elements and 152 I/O pins.

• FLEX devices combine the benefits of erasable programmable

logic devices (EPLDs) (i.e. high speed and predictable interconnect delays) and field programmable gate arrays (FPGAs) (i.e. fined grained structure and high register count).

Functional Description

• Large matrix of compact building blocks called logic elements

(LEs).

• Each LE consists of a 4 input LUT that provides the combinational

logic capability, and a programmable register to provide the sequential logic capability (similar to the macrocell block of the earlier families).

• LEs are grouped into sets of eight to create Logic Array Blocks

(LABs). Each LAB is an independent structure with common inputs, interconnections and control signals.

Department of Electrical and Computer Engineering

Slide 10

Robert Betz: 97

• I/O supported by IOEs (Input Output Elements) – located at the end
• f interconnection rows and columns. Contain bidirectional buffer

and a flip flop that can be used as either an input or output register.

Logic Array Block (LAB) Logic Element (LE) FastTrack Interconnect IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE

Figure 8 : Flex 8000 Device Block Diagram

Department of Electrical and Computer Engineering

Slide 11

Robert Betz: 97

Logic Elements

• Smallest element of logic in the Flex 8000. See Figure 9.
• Two dedicate high speed paths – carry and cascade chains, do not

use the general purpose interconnect. Carry for high speed counters and adders, cascade for wide input functions.

• Heavy use of the carry and cascade chains can restrict placement

and routing of other logic - should only be used for speed critical portions of the design.

• LEs can operate in a number of different modes, see Figure 10.

Data 1 Data 2 Data 3 Data 4 Clear/ Preset Logic LABCTRL1 LABCTRL2 D PRN CLRN LE Out LABCTRL3 LABCTRL4 Look-up Table (LUT) Carry Chain Cascade Chain Clock Select Carry-in Cascade-in Carry-out Cascade-out

Figure 9 : Flex 8000 Logic Element (LE)

Department of Electrical and Computer Engineering

Slide 12

Robert Betz: 97

D PRN CLRN 4-Input LUT Data 1 Data 2 Data 3 Data 4 Carry-In Cascade-Out Cascade-In LE-Out

Normal Mode

D PRN CLRN Cascade-Out LE-Out Cascade-In Data 1 Data 2 Carry-Out Carry-In

Arithmetic Mode

3-Input LUT LUT 3-Input D PRN CLRN LE-Out Cascade-In Carry-Out 3-Input LUT LUT 3-Input Cascade-Out Carry-In Data 1(ENA) Data 2 (U/D) Data 3 (Data) Data 4 (!LOAD)

Up/Down Counter Mode

D PRN CLRN Carry-Out 3-Input LUT LUT 3-Input Cascade-Out Carry-In Data 1(ENA) Data 2 (CLEAR) Data 3 (Data) Data 4 (!LOAD) 1 1 LE-Out

Clearable Counter Mode

Figure 10 : Logic element operating modes

Department of Electrical and Computer Engineering

Slide 13

Robert Betz: 97

• Clear and preset logic control - compiler selects the best control sig-

nal implementation during compilation.

• Preset can be provided by using Clear and inverting the output of

the register. Inversion control is available for the inputs to both the LEs and the IOEs.

D PRN CLRN Q LE-Out Data 3 LABCTRL1 LABCTRL2 Vcc

Clear Logic

D PRN CLRN Q LE-Out Vcc Data 3 LABCTRL1

Preset Logic

Figure 11 : Logic Element Clear and Preset Logic

Department of Electrical and Computer Engineering

Slide 14

Robert Betz: 97

Logic Array Block

• Logic Array Block (LAB) consists of eight LEs, their associated

carry and cascade chains, LAB control signals, and the LAB local interconnect.

• Provides the course grain structure of the architecture which allows

efficient routing with high device utilization and performance.

• Each LAB provides four control signals that can be used in all eight
• LEs. Two can be used as clocks and two as preset and clear. Pro-

grammable inversion is available on these signals. These signals provide very low clock skew to all the elements of the array.

• See Figure 12 for a block diagram of the logic array block.
• FastTrack Interconnect – connections between LEs and the device

I/O pins. Provides fast and predictable interconnection delays (dif- fers from FPGAs in this respect).

• See Figure 13 for the details of the row to column interconnect.
• Figure 14 shows the interconnect resources for the Flex 8000. Note

that inputs into the LAB have to come via a row. Also the column resources are very scarce, and are their use is closely supervised by the compiler.

• Figure 15 shows the row to IOE connections. Inputs from an IOE

can drive two separate row channels. When an IOE is used as an

• utput the signal is driven by an n-to-1 multiplexer that selects the

row channel. The size of the multiplexer varies with the number of columns in a device– e.g. some devices have 21-1 multiplexer, oth- ers a 27-1 multiplexer. Note that each pin has a limited row inter- connect – cannot interconnect to an arbitrary row channel.

Department of Electrical and Computer Engineering

Slide 15

Robert Betz: 97

Row Interconnect (168 channels) Column Interconnect (16 channels) LAB Local Interconnect (32 channels) 24 4 8 16 8 2 4 2 8 LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 Carry-Out and Cascade-Out to LAB on the right Carry-In & cascade-In from LAB

• n right

Dedicated Inputs 4 4 4 4 4 4 4 4 4 LAB control signals

Figure 12 : Logic Array Block

Column to row interconnect (see Figure 13 for details)

Department of Electrical and Computer Engineering

Slide 16

Robert Betz: 97

16 Column Channels 168 Row Channels

to local feedback to local feedback Each LE drives up to two column channels Each LE drives one row channel LE1 LE2

Figure 13 : LAB connections to row and column interconnect

Department of Electrical and Computer Engineering

Slide 17

Robert Betz: 97

IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE

Row Interconnect Column interconnect LAB A1 LAB B1 LAB LAB A2 B2

1 8 1 8 See Figure 17 for details See Figure 15 for details

Figure 14 : Flex 8000 device interconnect resources

Cascade and carry chain

Department of Electrical and Computer Engineering

Slide 18

Robert Betz: 97

IOE1 IOE2 IOE3 IOE4 IOE5 IOE6 IOE7 IOE8

2 2 2 2 n n n n n n n n 168(216) 168(216) 168(216) I/O line is driven by an n-to-1 MUX, where n is equal to the number of columns in the device Row Interconnect

Figure 15 : Flex 8000 row to IOE connection

2 2 2 2 2 2 2 2 See Figure 16 below for detail

IOE1 IOE8 Row (216) 168 Switches set by SRAM bits

Figure 16 : Detail of the IOE to row interconnect selection

Department of Electrical and Computer Engineering

Slide 19

Robert Betz: 97

• There are IOEs on the top and bottom of each column I/O intercon-

nect.

• The output of an 8-to-1 multiplexer is connected to each of the
• IOEs. See Figure 17.
• The Input-Output Elements (IOEs) themselves are a reasonably

complex circuit. They can be used for input, output or bidirectional I/O (See Figure 18).

• They are present at the ends of the row and column interconnects.
• Each I/O pin has a register that can be used for latching input data
• r output data.

IOE IOE

Each IOE is driven by an 8-to-1 multiplexer Each IOE can drive up to two column channels. 16 Column Interconnect

Figure 17 : Flex 8000 column to IOE connection

Department of Electrical and Computer Engineering

Slide 20

Robert Betz: 97

• Output buffers have an adjustable slew rate control so that one can

trade noise off against speed.

• The IOE can be controlled (i.e. clearing of the register, clocking of

the register) via a dedicated “peripheral bus” that skirts the whole chip.

D CLRN Q

Vcc Slew rate control Programmable inversion 2(8) I/O controls 2(8) 2(8) To row to column interconnect From row to column interconnect CLR0 CLR1/OE CLK0 CLK1/OE

Figure 18 : I/O element (IOE) for a typical Altera EPLD.

OE[0..1(7)]

Department of Electrical and Computer Engineering

Slide 21

Robert Betz: 97

• Signals for the peripheral bus can be generated by any of the 4 ded-

icated input lines, or signals on the row interconnect channels (the number of row channels corresponds to the number of columns in the device (i.e. 13, 21 or 27 depending on the device). See Figure 19

4 1 2 n Peripheral control signals OE[0..1(7)] CLR0 CLR1 CLK0 CLK1 Dedicated inputs Row channels

Figure 19 : Flex 8000 peripheral control bus

Department of Electrical and Computer Engineering

Slide 22

Robert Betz: 97

FPGA (Field Programmable Gate Array) Devices

• In many ways these devices are similar to the EPLD based devices.
• Main difference is the routing. The FPGA devices have a more flex-

ible routing system at the expense of having more routing delays.

• Modern FPGAs are still based on the use of logic blocks -Figure 20.

D SD Q RD EC SD D EC Q YQ XQ 1 1 S/R Control S/R Control EC Din/H2 SR/H0 H1 4 C1...C4 G4 G3 G2 G1 F1 F2 F3 F4 Din F’ G’ H’ H’ G’ H’ G’ F’ H’ F’ RD Din F’ G’ H’ Logic function of H’ , F’, G and H1’ Logic function

• f G1-G4

Logic function

• f F1-F4

K (Clock) X Bypass Multiplexer controlled by configuration program.

Figure 20 : Logic cell in XC4000 Xilinx FPGA.

Department of Electrical and Computer Engineering

Slide 23

Robert Betz: 97

Other features:

• The logic function blocks are implemented using RAM (as in

Altera), but they can also be configured as RAM cells for general use.

• Have I/O Blocks (similar to the Altera) which connect to the pins

and allow input and output into and out of the chip.

• Has internal tristate buffers so one can build tristate buses on the
• chip. Also has programmable pull-up resistors which allow wired

AND functions.

• The major difference between the FPGA and the CPLD (Complex

Programmable Logic Device) are the routing options available in the former. See Figure 21.

• Some nomenclature: Single means the lines run from one CLB

(Complex Logic Block) to the next and there is a connection block at each CLB, double means that there is a connection block every second CLB, quad means that there is a connection block every fourth CLB.

• The connection blocks allow any line to be connected to any other
• line. This is implemented via a switching matrix. Figure 22 shows a

conceptual view of the interconnect for the Xilinx FPGAs.

• The switch matrix is implemented as a set of six pass transistors.

The quad line interconnect have a switch matrix together with a buffer (provides a high speed line). Long lines (run the whole length and width of the chip) can be driven by tristate buffers to form chip wide buffers. See Figure 23.

Department of Electrical and Computer Engineering

Slide 24

Robert Betz: 97

CLB

Quad Long Global Clock Long Double Single Global Clock Carry Chain Double 12 4 4 6 4 8 4 2 12 8 4 3 2 3 Quad Single Double Long Direct Connect Direct Connect Long

Figure 21 : High-level routing diagram of the XC4000EX series CLB

CLB

Figure 22 : Xilinx crossbar connect

Switch matrix Programmable interconnect

Department of Electrical and Computer Engineering

Slide 25

Robert Betz: 97

Six pass transistor matrix

Figure 23 : Programmable switch matrix