Design and Architectures for Embedded Systems Prof. Dr. J. Henkel - - PDF document

SLIDE 1

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Design and Architectures for Embedded Systems

• Prof. Dr. J.
• Prof. Dr. J. Henkel

Henkel CES CES -

• Chair for Embedded Systems

Chair for Embedded Systems University of University of Karlsruhe Karlsruhe, Germany , Germany

Today: Introduction and Overview Today: Introduction and Overview

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Embedded Systems Examples

• Automotive

Automotive ABC, ABS, DSC, …

ABC, ABS, DSC, …

• Banking&Money transfer

Banking&Money transfer smart cards, …

smart cards, …

• Consumer

Consumer cell phone, DVD player, MP3

cell phone, DVD player, MP3 player, PDA, … player, PDA, …

• Clothing

Clothing electronic textiles

electronic textiles

• Environment

Environment sensor networks

sensor networks

• Healthcare

Healthcare hearings aids, pace maker, …

hearings aids, pace maker, …

• Home Appliances

Home Appliances microwave oven,

microwave oven, dishwasher, … dishwasher, …

• Home Automation

Home Automation EIB, X10, …

EIB, X10, …

• Office Automation

Office Automation fax, printer, …

fax, printer, …

• Security

Security screening, surveillance systems, …

screening, surveillance systems, …

• Telecom Systems

Telecom Systems satellite, …

satellite, …

• Test and Measurement Equipment

Test and Measurement Equipment

Ampere/Volt Ampere/Volt-

• meter, Logic analyzer, …

meter, Logic analyzer, …

SLIDE 2

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Example 1 for an Embedded System: Settop Box Chip

• System

System-

• On

On-

• a

a-

• Chip:

Chip: uP uP, , caches, ASIC, main caches, ASIC, main memory, I/O memory, I/O

• Today’s Technology:

Today’s Technology: 0.18u … 0.07u 0.18u … 0.07u -

• > >>

> >> 100 million 100 million transistors/chip possible transistors/chip possible

• Practice: < 100million

Practice: < 100million transistors transistors

• why ?

why ?

• > “productivity gap”

> “productivity gap”

MPEG Macro (core) uP Cache

(source:NEC Japan)

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Example 2: E-Textiles

• Smart Shirt -

]

Source: [Marc03]

SLIDE 3

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Example 3: Medical Diagnostics

(source: Jan Madsen DTU)

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Example 4: Sensor Networks

Manufacturing plants & Power distribution

• Improve reliability, operating efficiency

Health care

• Unwired operating

rooms

• Early detection of

cardiac attacks Energy-efficient buildings

• $55 B / year
• pportunity in the

US

Disaster Prevention & Emergency Response

Traffic control

• Reduce commute time

by 15 min => $15B/year in California alone “Smart” environments

• Homes, Offices, Schools, …
• Convenience, Productivity, Security

(source: A. Raghunathan, NEC)

SLIDE 4

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Embedded System Definition

• There is no concise definition of an embedded system

There is no concise definition of an embedded system

• But here are some common characteristics …

But here are some common characteristics …

• specialized to an application domain, single application or spec

specialized to an application domain, single application or specific ific task (=> less flexible but probably more efficiently to design) task (=> less flexible but probably more efficiently to design)

• Underlies many and tight constraints (later)

Underlies many and tight constraints (later)

• Designing an embedded system is typically more challenging than

Designing an embedded system is typically more challenging than designing a general designing a general-

• purpose computer

purpose computer

• Interacts with the real world => designing embedded software

Interacts with the real world => designing embedded software requires the consideration of more constraints than designing requires the consideration of more constraints than designing software for general software for general-

• purpose computers

purpose computers

• By far higher volume than general

By far higher volume than general-

• purpose computers. Example: a

purpose computers. Example: a single luxury car has already >100 embedded systems single luxury car has already >100 embedded systems

• Market revenue for ES is by far higher than it is for general

Market revenue for ES is by far higher than it is for general-

• purpose computers (billions instead of millions)

purpose computers (billions instead of millions)

• New application areas evolve each day …

New application areas evolve each day …

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Moore’s Law

• Gordon E. Moore (co

Gordon E. Moore (co-

• founded Intel in 1968)

founded Intel in 1968)

• Prediction in 1965:

Prediction in 1965:

• Exponential growth of number of transistors per

Exponential growth of number of transistors per chip chip

• Initial observation: Complexity per die area will

Initial observation: Complexity per die area will double about every year double about every year

• Was later relaxed to “doubling every 18 months”

Was later relaxed to “doubling every 18 months”

• This trend will continue for foreseeable future

This trend will continue for foreseeable future

• Original paper:

Original paper: “ “Cramming more components onto integrated circuits”, Electronics, Volume 38, Number 8, April 19, 1965

• 2003:

2003: “ “No exponential is forever No exponential is forever … … but we can delay but we can delay ‘ ‘FOREVER FOREVER’ ’ ” ”, talk , talk by G. E. Moore at by G. E. Moore at International Solid State Circuits Conference International Solid State Circuits Conference (ISSCC) (ISSCC), Feb. 2003. , Feb. 2003.

• For more info: International Technology Roadmap for Semiconducto

For more info: International Technology Roadmap for Semiconductors: rs: http://public. http://public.itrs itrs.net .net

(source: Intel)

• Jan. 1971: Intel's

4004 chip; 2,200 transistors; a 4-bit microprocessor; it addressed 9.2 K of memory

SLIDE 5

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Visualization of Moore’s Law

• 1970: 1k DRAM (introduced by Intel)

1970: 1k DRAM (introduced by Intel)

• 2005: 4G DRAM (150nm)

2005: 4G DRAM (150nm)

• 2010: 64G DRAM (80nm)

2010: 64G DRAM (80nm)

1970 1970 soccer field soccer field size size 2005 2005 less than credit card size less than credit card size Factor 2^22 Factor 2^22 i.e. 4 million i.e. 4 million

• Note: exponential growth is larger than many people conceive!

Note: exponential growth is larger than many people conceive!

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Design Productivity Gap

Transistors / Chip (w/o memory) Transistors / Staff-month

100 1000 10000 100000 1000000 10000000 100000000 1981 1985 1989 1993 1997 2001 2005 2009

10 1000

Moore’s Law Gap Limit to adding more skilled Engineers Engineering Productivity Trend

10000000 100000

(source: [KeBri98]

SLIDE 6

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Complexity of Microprocessors

(source: Intel)

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Trends: Crisis of Complexity

55 50 47 43 32 25 20 10 8 3 2 1 0.8 0.4 0.3 0.2

50 100 150 200 250 300

Available Gates Used Gates

Millions of Gates 1990 1992 1994 1996 1998 2000 2002 2004 2006

Design Productivity Gap

[source: Gartner/Dataquest]

Prediction for the case no ESLTools will be used However: red curve will apply And lead to SoCs with 100s –1000s of PEs per chip

SLIDE 7

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Design Metrics

• Performance

Performance often the most prominent metric

• ften the most prominent metric
• Power consumption

Power consumption important for mobile battery

important for mobile battery-

• driven devices

driven devices

• Size (chip area, code size)

Size (chip area, code size)

• Cost per unit

Cost per unit

• NRE cost: non

NRE cost: non-

• reoccurring engineering costs

reoccurring engineering costs

• Flexibility

Flexibility how much effort is it to update/modify the design?

how much effort is it to update/modify the design?

• Testability

Testability can the system be tested with reasonable effort?

can the system be tested with reasonable effort?

• Maintainability

Maintainability how much effort is it to operate/repair the system?

how much effort is it to operate/repair the system?

• Reliability

Reliability how reliable is the design under changing environmental and

how reliable is the design under changing environmental and

• perating conditions over time?
• perating conditions over time?
• …

…

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Performance

There are many definitions definitions for performance … There are many definitions definitions for performance …

• Speedup

Speedup

• Speedup of processor ‘A’ over ‘B’. S = throughput_A / throughput

Speedup of processor ‘A’ over ‘B’. S = throughput_A / throughput_B _B

• Throughput

Throughput

• In a pipeline: rate at which data is produced (maximum: 1/T_

In a pipeline: rate at which data is produced (maximum: 1/T_cyc cyc) )

• Throughput of a system can be increased through concurrency

Throughput of a system can be increased through concurrency

• Latency

Latency

• Time it takes to produce a result (‘response time’)

Time it takes to produce a result (‘response time’)

• Circuit latency: Ex: time to execute a sequence of instructions

Circuit latency: Ex: time to execute a sequence of instructions (measured (measured in # clock cycles) in # clock cycles)

• Cycle Time

Cycle Time

• Sequential logic: fastest clock that can be applied to a circuit

Sequential logic: fastest clock that can be applied to a circuit determines determines the cycle time T_ the cycle time T_cyc cyc

• Propagation Delay

Propagation Delay

• Combinational logic: I/O propagation delay

Combinational logic: I/O propagation delay

SLIDE 8

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Power Consumption

• Many embedded systems are

Many embedded systems are battery battery-

• driven; some of them cannot

driven; some of them cannot be recharged for entire life time be recharged for entire life time

• Power efficiency is an important

Power efficiency is an important characteristic: e.g. MHz/ characteristic: e.g. MHz/mW mW (see (see data sheets of embedded data sheets of embedded processors) processors)

• Power consumers in an embedded

Power consumers in an embedded system system

• Hardware: CPU. memory hierarchy,

Hardware: CPU. memory hierarchy, communication (buses etc) communication (buses etc)

• Software: application program, RTOS, …

Software: application program, RTOS, …

• Peripherals: sensors, actuators, …

Peripherals: sensors, actuators, …

• Power Optimization strategies (at design and/or operating time)

Power Optimization strategies (at design and/or operating time)

• Silicon technology, synthesis, micro

Silicon technology, synthesis, micro-

• architecture, RTOS, power

architecture, RTOS, power management, compiler, algorithms, … management, compiler, algorithms, …

Example for an evenly and unevenly discharged battery: the total capacity of the battery might vary = > can be exploited by power saving strategies current [A] Time Energy ~ S I(t) dt != const T_a T_b

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Product life cycle for semiconductors

revenue Time (typically years) Market entry Peak volume Product life cycle Generation 0 Generation 1 Generation 2

• Each generation marks a new silicon technology

Each generation marks a new silicon technology

• Life cycles are overlapping

Life cycles are overlapping

• Area under a curve refers to total

Area under a curve refers to total generated revenue for a chip generation generated revenue for a chip generation

SLIDE 9

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Time to Market

• Time to market: from idea to product

Time to market: from idea to product

• Time to market is key:

Time to market is key:

• Delayed time to market significantly reduces revenue (might

Delayed time to market significantly reduces revenue (might produces losses in fact) produces losses in fact)

• In some cases: if market entry is too early: market might not be

In some cases: if market entry is too early: market might not be ready for product ready for product

• reduced peak volume

reduced peak volume

• significantly smaller

significantly smaller total revenue total revenue

revenue Time (typically years) Delayed market entry Company A Company B

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Cost

• NRE cost

NRE cost

• Non

Non-

• reoccurring engineering cost: one

reoccurring engineering cost: one-

• time cost of a new product

time cost of a new product (e.g. R&D etc) (e.g. R&D etc)

• Recently, NRE cost of newest deep sub

Recently, NRE cost of newest deep sub-

• micron technologies (0.1u

micron technologies (0.1u and beyond) became very large and beyond) became very large ⇒ ⇒Volume needs to be very high to amortize costs Volume needs to be very high to amortize costs This trend has a significant impact on the design of embedded This trend has a significant impact on the design of embedded systems (e.g. dropping number of ASIC design starts) systems (e.g. dropping number of ASIC design starts)

• Cost per unit

Cost per unit

• Cost_unit = (NRE_cost + #units * cost_of_one_unit) / #units

Cost_unit = (NRE_cost + #units * cost_of_one_unit) / #units

• The sales price be higher than the cost of one unit

The sales price be higher than the cost of one unit

• The sales price will be determined by the market (e.g. competito

The sales price will be determined by the market (e.g. competitors) rs)

SLIDE 10

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Cost (cont’d)

1997 1998 1999 2002 technology 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Technology [micron] technology 0.35 0.25 0.18 0.13 1997 1998 1999 2002

Fab cost: ~$2.5bn design cyc: 10-12mo complex.: 1-2M apps: set-top box, wireless PDA Fab cost: >$4bn design cyc: 6-8mo complex.: 10-25M apps: ? Fab cost: ~$3.5bn design cyc: 8-10mo complex.: 4-6M apps: IAs,

• anyth. portable

Fab cost: ~$1.5bn design cyc: 12-18mo complex.: 200-500k apps: cell ph, PDAs, DVD, etc

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

NRE cost and volume

• Varying NRE costs due to:

Varying NRE costs due to:

• Different silicon technology

Different silicon technology

• Longer design time (e.g. time to refine the design)

Longer design time (e.g. time to refine the design)

• Deployed design tools

Deployed design tools

• …

…

• Higher NRE cost may result in lower cost per produced unit

Higher NRE cost may result in lower cost per produced unit

• Total cost depend on volume

Total cost depend on volume

100000 200000 300000 400000 500000 600000 50 100 150 200 250 300 350 400 450 500 in 1000 units total cost

NRE = 200,000; unit costs = 100 NRE = 50,000; unit cost = 500 NRE = 10,000; unit cost = 1,000

SLIDE 11

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Chip area

• Chip area is not the major design constraint any more

Chip area is not the major design constraint any more

• At the end of this decade it will be possible to integrate a

At the end of this decade it will be possible to integrate a billion (10^9) transistors on a single piece of silicon billion (10^9) transistors on a single piece of silicon

• Often, time

Often, time-

• to

to-

• market is that stringent that chip area is

market is that stringent that chip area is sacrificed (trade sacrificed (trade-

• off)
• ff)
• Chip complexity is often measured in gate equivalents:

Chip complexity is often measured in gate equivalents:

⇒ ⇒ the basic unit of measure of a digital logic circuit complexity. the basic unit of measure of a digital logic circuit complexity. Gate equivalent is the number of individual logic gates that Gate equivalent is the number of individual logic gates that would have to be connected to perform the same function would have to be connected to perform the same function

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Interdependency of design metrics

CPU DSP

ASIC1 ASIC2 bus1 bus2 bus3

chip size power perf cost

• Constraints may by

Constraints may by contradictory contradictory

• Example: high performance

Example: high performance requires latest technology requires latest technology and thus will be quite and thus will be quite expensive expensive

• A real

A real-

• world solution is

world solution is always a always a compromise compromise between various design between various design constraints constraints

• It is an art to weigh various

It is an art to weigh various constraints against each constraints against each

• ther and to find the best
• ther and to find the best

compromise between all compromise between all possible solutions (I.e. possible solutions (I.e. design space) design space)

SLIDE 12

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Columns of Embedded System Design

• Electronic system

Electronic system-

• level design

level design (ESL) methodologies (ESL) methodologies

• Raising complexity of systems

Raising complexity of systems-

• on
• n-
• chip (SOC) requires design

chip (SOC) requires design methodologies at higher level of abstraction methodologies at higher level of abstraction

• The large design space to be efficiently explored

The large design space to be efficiently explored

• Embedded processor

Embedded processor architectures architectures

• General

General-

• purpose computer architectures are hardly appropriate for

purpose computer architectures are hardly appropriate for ES since they offer a fair compromise between many constraints ES since they offer a fair compromise between many constraints but they do not allow to adapt to the specific needs for ES but they do not allow to adapt to the specific needs for ES

• Embedded

Embedded Software Software

• Technology

Technology of integrated circuits

• f integrated circuits
• New technologies offer new possibilities for ES design

New technologies offer new possibilities for ES design

• Example: reconfigurable computing due to advances in FPGA

Example: reconfigurable computing due to advances in FPGA technology technology

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

General-purpose processor, ASIP, ASIC

Flexibility, 1/time-to-market, … “efficiency”: $/Mips, mW/MHz, Mips/area, … ASI C:

• Non-programmable,
• highly specialized

ASI C:

• Non-programmable,
• highly specialized

General purpose processor General purpose processor ASI P (extensible processor) ASI P (extensible processor)

• instruction extension/ definition
• parameterization
• inclusion/ non-inclusion of

functionality/ devices “Hardware solution” “Software solution”

SLIDE 13

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

General-purpose Processor

• Features

Features

• Fully programmable

Fully programmable

• General

General-

• purpose

purpose ALU, FPU etc ALU, FPU etc

• For ‘any’ application

For ‘any’ application

• General

General-

• purpose

purpose instruction set instruction set

• Non

Non-

• extensible

extensible

• High SW flexibility

High SW flexibility

• Un

Un-

• expensive

expensive

• …

…

Data path General-purpose Processor Control path Control logic State registers PC IR Register file ALU, FPU Program memory Data memory

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

ASIP, Extensible Processor

• Features

Features

• Fully Programmable

Fully Programmable

• General purpose or

General purpose or specialized ALU, FPU, specialized ALU, FPU,

• Adapted to an

Adapted to an application domain (e.g. application domain (e.g. multimedia) multimedia)

• Instruction may be

Instruction may be extensible extensible

• Good software flexibility

Good software flexibility

• Relatively expensive

Relatively expensive since lower volume since lower volume

Data path Control path Control logic State registers

• Extensible

instruction set

• special

registers

• additional

ALU’s etc. PC IR Register file ALU, FPU Program memory Data memory ASIP , Extensible Processor

SLIDE 14

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Accelerator, ASIC

• Features

Features

• A very specialized

A very specialized ‘Processor”, only for one ‘Processor”, only for one application application

• Hardwired (no instruction

Hardwired (no instruction set) set)

• Very expensive (needs

Very expensive (needs high volume) high volume)

• Unsurpassed efficiency

Unsurpassed efficiency

• Low power

Low power

• High performance

High performance

• …

…

Data path Accelerator (ASIC) Control path Control logic State registers Register file ALU, FPU Data memory

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Design Methodology

System Spec Behavioral Spec Register-transfer (RT) Spec Logic Spec System synthesis

• Behav. Synthesis

RT synthesis Logic Synthesis Platforms (SW. HW, OS, firmware) IP cores RT components gates

Abstraction level Synthesis IP

Hardware only Hardware and software

SLIDE 15

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Co-Design of hardware and software

• Hardware and

Hardware and software are no longer software are no longer developed separately developed separately

• Basic techniques in

Basic techniques in SW and SW are SW and SW are matured and can be matured and can be used to concurrently used to concurrently design hardware and design hardware and software software

=> hardware/software co => hardware/software co-

• design

design

Implementation Assembly instructions Machine instructions Register transfers Compilers (1960's,1970's) Assemblers, linkers (1950's, 1960's) Behavioral synthesis (1990's) RT synthesis (1980's, 1990's) Logic synthesis (1970's, 1980's) Microprocessor plus program bits: “software” VLSI, ASIC, or PLD implementation: “hardware” Logic gates Logic equations / FSM's Sequential program code (e.g., C, VHDL)

The “co-design ladder” by F. Vahid

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

ESL Design Methodologies

• What?

What? -

• > ESL: Electronic System

> ESL: Electronic System-

• level design

level design

• (Co)

(Co)-

• Synthesis, (co)

Synthesis, (co)-

• simulation, verification, …

simulation, verification, …

• Design a whole system rather than single un

Design a whole system rather than single un-

• adapted components

adapted components

• Why?

Why?

• Complexity of future embedded can systems may not be handled (‘g

Complexity of future embedded can systems may not be handled (‘gap’) ap’)

• Optimize with system component interdependencies in mind

Optimize with system component interdependencies in mind

• How?

How?

• Need to raise the abstraction level: Functionality rather than

Need to raise the abstraction level: Functionality rather than implementation (i.e. HW, SW. firmware) implementation (i.e. HW, SW. firmware)

• Benefits?

Benefits?

• Fast design space exploration

Fast design space exploration

• Allows to build complex designs and thus to make use available s

Allows to build complex designs and thus to make use available silicon ilicon technology technology

SLIDE 16

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

ESL Design Methodologies Example: MPEG-2 video Encoder

Instruction cache size (2x)

MPEG-2 video encoder

Software I-cache D-cache Memory

90 50 10 Energy percentage ( %)

CPU1 CPU1 Main Memory Main Memory Communication: Communication: (buses, on (buses, on-

• chip network)

chip network) Caches Caches I/O I/O CPU2 CPU2 DSP1 DSP1 CPU1 CPU1 CPU1 CPU1 Main Memory Main Memory Main Memory Main Memory Communication: Communication: (buses, on (buses, on-

• chip network)

chip network) Communication: Communication: (buses, on (buses, on-

• chip network)

chip network) Caches Caches Caches Caches I/O I/O I/O I/O CPU2 CPU2 CPU2 CPU2 DSP1 DSP1 DSP1 DSP1

A simple architecture Power/ performance Breakdown ESL Design Flow

(source: [HeLi02])

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Embedded Software

• “Classical Software”

“Classical Software”

• Software is the realization of mathematical functions as procedu

Software is the realization of mathematical functions as procedures res

• A set of input data is mapped into a set of output data

A set of input data is mapped into a set of output data

• The mechanism that executes the procedures is not as important

The mechanism that executes the procedures is not as important as the abstract properties of the functions as the abstract properties of the functions

• In theory, the mechanism can be implemented by a Turing

In theory, the mechanism can be implemented by a Turing machine machine

• See also [Lee01]

See also [Lee01]

• Embedded Software is different

Embedded Software is different

• Interaction with the real world is most important

Interaction with the real world is most important

SLIDE 17

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Embedded Software Properties

• Example: an software of an Anti

Example: an software of an Anti-

• lock Braking System, ABS,

lock Braking System, ABS, in a car in a car

• The ABS software should be able to:

The ABS software should be able to:

• react to driver pushing the brake pad =>

react to driver pushing the brake pad => REACTIVITY REACTIVITY

• stop the car before hitting the tree

stop the car before hitting the tree -

• >

> TIMELINESS TIMELINESS

• monitor wheel RPM while actuating brakes =>

monitor wheel RPM while actuating brakes => CONCURRENCY CONCURRENCY

• handle the next situation after the completed the current one

handle the next situation after the completed the current one => => LIVENESS LIVENESS

• …

…

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Embedded Software (cont’d)

• Timeliness

Timeliness

• Computation does take time; needs to be considered when design

Computation does take time; needs to be considered when design ES ES

• Concurrency

Concurrency

• ES interacts typically with more than one physical process => mu

ES interacts typically with more than one physical process => must st be able to react simultaneously be able to react simultaneously

• Liveness

Liveness

• ES must not terminate or block waiting for events that won’t occ

ES must not terminate or block waiting for events that won’t occur ur

• Reactivity

Reactivity

• React continuously to events in the physical world

React continuously to events in the physical world

• Heterogeneity

Heterogeneity

• ES implementation is typically a mix of computational and

ES implementation is typically a mix of computational and implementational implementational styles styles

• Heterogeneous event handling styles

Heterogeneous event handling styles

SLIDE 18

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

IC technologies

uP, DSP, … standard System components I/O, Graphic, … ROM DRAM, SRAM,… PROM, EPROM, EEPROM, … PLD, EPLD, EEPLD, … semi- custom full- custom Gate- Array, Sea of Gates Standard-/ Macro Cells PGAs XILINX, Actel, … Standard-ICs Application-specific ICs hard-wired mask- programmable custom programmable application- specific

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Custom vs. Semicustom

• Custom

Custom

• Functional and physical design are handcrafted

Functional and physical design are handcrafted

• High potential for optimization

High potential for optimization

• But: extensive effort

But: extensive effort

• Semi

Semi-

• custom

custom

• Restricting # of circuit primitives

Restricting # of circuit primitives

• Smaller optimization potential

Smaller optimization potential

• Focus is on interconnection of primitives

Focus is on interconnection of primitives

• Restriction makes it easier to develop CAD tools

Restriction makes it easier to develop CAD tools

• A larger number of implementation choices can be explored throug

A larger number of implementation choices can be explored through h usage of efficient CAD tools usage of efficient CAD tools

SLIDE 19

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Semi-custom Design Styles

Cell-based Array-based Standard cells Macro cells Pre-diffused Pre-wired

Memory, PLA, … Gate Array, Sea of Gates, … Anti-fuse, …

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Semi-custom Design Styles (cont’d)

• Standard cells:

Standard cells:

• From a library (

From a library (param param: technology, area, delay, voltage, …) : technology, area, delay, voltage, …) -

• >

> large large -

• > high maintenance

> high maintenance

• Macro cells (“building blocks”)

Macro cells (“building blocks”)

• Module/cell generators: do placing + wiring when functional

Module/cell generators: do placing + wiring when functional description is given description is given

• Exmpl

Exmpl: : PLAs PLAs ( (Progr

• Progr. Logic Arrays)

. Logic Arrays)

• Compatibility w/ custom components (combining) like done in

Compatibility w/ custom components (combining) like done in uP uP design design

• Array

Array-

• based

based

• Matrix of “

Matrix of “uncommited uncommited components”. They are personalized and components”. They are personalized and connected (i.e. FPGA) connected (i.e. FPGA)

• Technologies: mask programmable, field programmable

Technologies: mask programmable, field programmable

SLIDE 20

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Dies of semi-custom design styles

(src: DeMi94)

FPGA Mask progr. gate array Applic.-specific using macro cells

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Comparison of semi-custom techn.

Custom Cell-base Pre-diffused Pre-wired Density very high high high med-low Perform. very high high high med-low Flexibility very high high medium low Design Time very long short short very short

• Manuf. Time

medium medium short ver short Cost: low vol. very high high high low Cost: high vol. low low low high

SLIDE 21

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Sneak Preview

• Emb. Software

Optimization for:

• low power
• Performance
• Area, …

Embedded Processor Design

• extens. Instruction
• Parameterization
• …

Integration Hardware Design

• synthesis

Middleware, RTOS

• Scheduling

System specification Design space exploration

• low power
• Performance
• Area
• …

System partitioning

• models of computation
• Spec languages

Estimation&Simulation

• low power
• performance
• Area, …

Tape out Prototyping

embedded IP:

• PEs
• Memories
• Communication
• Peripherals
• …

IC technology

Optimization

• low power
• performance
• Area, …

refine

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

Summary

• Embedded systems are ubiquitous

Embedded systems are ubiquitous

• Future embedded systems will be of large complexity, low

Future embedded systems will be of large complexity, low power, tiny sized, low cost, … (=> ambient) power, tiny sized, low cost, … (=> ambient)

• Key: ESL design methodologies, embedded architectures,

Key: ESL design methodologies, embedded architectures, IC technologies IC technologies

• The border between hardware and software is blurred. HW

The border between hardware and software is blurred. HW and SW are designed together (HW/SW co and SW are designed together (HW/SW co-

• design)

design)

• Embedded system’s designer

Embedded system’s designer

• Skills from two core groups are needed” Computer Science and

Skills from two core groups are needed” Computer Science and Engineering Engineering

• Diversity is very high: design methodologies, architectures,

Diversity is very high: design methodologies, architectures, compilers, IC technology, … compilers, IC technology, …

SLIDE 22

• J. Henkel, Univ. of Karlsruhe, SS 2004

http://ces.univ-karlsruhe.de

References and Sources

• [Lee01] E.A.Lee, “Embedded Software”, M. Selkowitz (Ed.) in Advances in Computers, Vol. 56,

Academic Press, London, 2002.

• [Marc03], Marculescu, D.; Marculescu, R.; Park, S.; Jayaraman, S.;

“Ready to ware”, Spectrum, IEEE ,Volume: 40 , Issue: 10 , Oct. 2003, Pages:28 - 32

• [Vahid02] F. Vahid, T. Givargis, Embedded System Design, John Wiley&Sons, 2002.
• [HeLi02] Henkel, J.; Yanbing Li, “Avalanche: an environment for design space exploration and
• ptimization of low-power embedded systems, Very Large Scale Integration (VLSI) Systems, IEEE

Transactions on ,Volume: 10 , Issue: 4 , Aug. 2002, Pages:454 - 468