Design and Architectures for Embedded Systems (ESII) Prof. Dr. J. - - PowerPoint PPT Presentation

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Design and Architectures for Embedded Systems (ESII) Prof. Dr. J. - - PowerPoint PPT Presentation

Jan 21, 2024 449 likes •831 views

1 ESII: Specification & Modeling Design and Architectures for Embedded Systems (ESII) Prof. Dr. J. Henkel, M. Shafique Prof. Dr. J. Henkel, M. Shafique CES CES - Chair for Embedded Systems Chair for Embedded Systems Karlsruhe Institute

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SLIDE 1
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 1 ESII: Specification & Modeling

Design and Architectures for Embedded Systems (ESII)

  • Prof. Dr. J. Henkel, M. Shafique
  • Prof. Dr. J. Henkel, M. Shafique

CES CES - Chair for Embedded Systems Chair for Embedded Systems Karlsruhe Institute of Technology, Germany Karlsruhe Institute of Technology, Germany

Today: Specification and Modeling II Today: Specification and Modeling II

  • Model and system properties

Model and system properties -

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SLIDE 2
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 2 ESII: Specification & Modeling

Embedded Processor Design & Architectures

Where are we?

  • models of computation
  • Spec languages

embedded IP:

  • PEs
  • Memories
  • Communication
  • Peripherals
  • …

IC technology

Optimization

  • low power, performance,

area, reliability, peak temp. …

Design Space Exploration Design Space Exploration

  • low power, performance, area, reliability,…
  • 8. ASIPs, Extensible
  • 8. ASIPs, Extensible

Processors Embedded Embedded Software Optimize for

  • Optimize for
  • Low Power
  • Performance
  • Area
  • Reliability
  • 7. ISA extensions 
  • 7. ISA extensions 

Special Instructions

  • 6. Code
  • 6. Code

Generation for Embedded Systems Middleware, Middleware, RTOS 13 & 14. 13 & 14. Scheduling

  • 9. DSPs, VLIW
  • 9. DSPs, VLIW

10 & 11. Reconfigurable 10 & 11. Reconfigurable Processors SYSTEM PARTITIONING SYSTEM PARTITIONING Hardware Hardware Design

  • Synthesis

2, 3, 4, 5 SYSTEM SPECIFICATION 2, 3, 4, 5 SYSTEM SPECIFICATION

refine

  • Integration
  • Integration
  • Prototyping
  • Tape out

Estimation&Simulation

  • low power, performance,

area, reliability, peak temp. …

  • 12. Multi-Corefuture
  • 12. Multi-Corefuture
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SLIDE 3
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 3 ESII: Specification & Modeling

Outline

 Rugby Meta Model Rugby Meta Model  Case Study A Design Project Case Study A Design Project

(src: A. Jantsch)

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SLIDE 4
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 4 ESII: Specification & Modeling

The Rugby Meta-Model

Abstraction in four domains Computation Communication Time Data

(src: A. Jantsch)

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SLIDE 5
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 5 ESII: Specification & Modeling

Example of a hierarchy

(src: A. Jantsch)

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SLIDE 6
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 6 ESII: Specification & Modeling

Example of an abstraction

(src: A. Jantsch)

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SLIDE 7
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 7 ESII: Specification & Modeling

Ways to handle complexity

(src: A. Jantsch)

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SLIDE 8
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 8 ESII: Specification & Modeling

Hierarchy, Abstraction, Domain

(src: A. Jantsch)

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SLIDE 9
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 9 ESII: Specification & Modeling

Rugby

(src: A. Jantsch)

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SLIDE 10
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 10 ESII: Specification & Modeling

Domains in Rugby

(src: A. Jantsch)

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SLIDE 11
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 11 ESII: Specification & Modeling

Computation Domain

(src: A. Jantsch)

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SLIDE 12
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 12 ESII: Specification & Modeling

An MOS transistor model

(src: A. Jantsch)

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SLIDE 13
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 13 ESII: Specification & Modeling

A transistor as switch

(src: A. Jantsch)

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SLIDE 14
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 14 ESII: Specification & Modeling

An AND gate as transistor network

 Two problems with arbitrary transistor networks:

 Output is not defined when input is 0.  Voltage drop between drain and source is relevant but not visible. that means, the model has not enough details in order to describe correctly the desired behavior

(src: A. Jantsch)

We can restrict the transistor network to a small number of patterns that Can be combined in arbitrary networks w/o violating assumption of switch-based transistor model

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SLIDE 15
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 15 ESII: Specification & Modeling

An Inverter as transistor network

(src: A. Jantsch)

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SLIDE 16
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 16 ESII: Specification & Modeling

Gate-based abstraction level

1. The primitive elements are defined by simple models, i.e. small truth tables in this case. 2. The primitive elements can be implemented in a wide range of technologies. 3. The model holds even for arbitrarily large networks of primitive elements.

(src: A. Jantsch)

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SLIDE 17
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 17 ESII: Specification & Modeling

Algorithms, Functions, Relations

(src: A. Jantsch)

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SLIDE 18
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 18 ESII: Specification & Modeling

Sorting defined as a relation

(src: A. Jantsch)

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SLIDE 19
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 19 ESII: Specification & Modeling

Sorting defined as a function

(src: A. Jantsch)

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SLIDE 20
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 20 ESII: Specification & Modeling

Sorting defined as algorithms

(src: A. Jantsch)

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SLIDE 21
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 21 ESII: Specification & Modeling

The communication domain

(src: A. Jantsch)

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SLIDE 22
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 22 ESII: Specification & Modeling

Communication at layout and gate level

(src: A. Jantsch)

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SLIDE 23
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 23 ESII: Specification & Modeling

Communication between processes

(src: A. Jantsch)

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SLIDE 24
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 24 ESII: Specification & Modeling

The data domain

(src: A. Jantsch)

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SLIDE 25
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 25 ESII: Specification & Modeling

The time domain

(src: A. Jantsch)

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SLIDE 26
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 26 ESII: Specification & Modeling

Notation for abstraction levels

computation communication data time

(src: A. Jantsch)

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SLIDE 27
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 27 ESII: Specification & Modeling

Abstraction levels in design phases

(src: A. Jantsch)

design phases domains

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SLIDE 28
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 28 ESII: Specification & Modeling

Design activities in terms of abstraction levels

(src: A. Jantsch)

Note: Design activities typically make design decisions and thus refine the design into a model at a lower abstraction level But: analysis activities do not refine models

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SLIDE 29
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 29 ESII: Specification & Modeling

Analysis activities in terms of abstraction levels

(src: A. Jantsch)

Analysis: check for consistency,; produce estimates;

  • In early design phases -> check for given requirements, for mutual

consistency or infer more detailed constraints

  • May also check feasibility
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SLIDE 30
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 30 ESII: Specification & Modeling

The network terminal case study

(src: A. Jantsch)

CPN: customer premises network

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SLIDE 31
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 31 ESII: Specification & Modeling

The network terminal case study (cont’d)

(src: A. Jantsch)

  • Traffic model: based on Asynchronous Transfer Mode (ATM)
  • ATM: virtual channels can share the same physical transport

Medium (like fiber)

  • ATM switch routes data packets from different virtual channels in the access network to the

respective CPN interface and vice versa

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SLIDE 32
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 32 ESII: Specification & Modeling

The NT design flow

(src: A. Jantsch)

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SLIDE 33
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 33 ESII: Specification & Modeling

Models in the NT design

(src: A. Jantsch)

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SLIDE 34
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 34 ESII: Specification & Modeling

The network terminal case study (cont’d)

(src: A. Jantsch)

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SLIDE 35
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 35 ESII: Specification & Modeling

Transformations in the NT design

(src: A. Jantsch)

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SLIDE 36
  • J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu 36 ESII: Specification & Modeling

References and Sources

 [Vahid02] F. Vahid, T. Givargis, Embedded System Design, John Wiley&Sons, 2002.  [BLee00] B. Lee, Specification and Design of Reactive Systems, PhD Dissertation, UC Berkeley, Spring 2000.  [A. Jantsch] A. Jantsch, “Modeling Embedded Systems and SoCs”, Morgan Kaufmann Publishers, 2004.