Design and Architectures for Design and Architectures for Embedded - - PowerPoint PPT Presentation

1

ESII: Intro and Overview

Design and Architectures for Design and Architectures for Embedded Systems (ESII) Embedded Systems (ESII)

• Prof. Dr. J. Henkel, M. Shafique
• Prof. Dr. J. Henkel, M. Shafique

CES CES - Chair for Embedded Systems Chair for Embedded Systems y Karlsruhe Institute of Technology, Germany Karlsruhe Institute of Technology, Germany

Today: Introduction and Overview Today: Introduction and Overview y

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

2

ESII: Intro and Overview

Organization

Contact: Contact: muhammad shafique@kit edu muhammad shafique@kit edu

Organization

Contact: Contact: muhammad.shafique@kit.edu muhammad.shafique@kit.edu Haid Haid-

• und

und-

• Neu

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• Str. 7
• Str. 7

Bld Bld 07.21, 07.21, Rm Rm 317.1 317.1 htt // it kit d / h fi / htt // it kit d / h fi / http://ces.itec.kit.edu/~shafique/ http://ces.itec.kit.edu/~shafique/ Homepage: Homepage: http://ces.itec.kit.edu/ http://ces.itec.kit.edu/ teaching/ES teaching/ES II w1011/ II w1011/ teaching/ES teaching/ES-II_w1011/ II_w1011/ Lecture time: Lecture time: Thu., 11:30 Thu., 11:30 – – 13:00 13:00 Bld 50 34 Multimedia R 102 Bld 50 34 Multimedia R 102

• Bld. 50.34, Multimedia R.102
• Bld. 50.34, Multimedia R.102

Examine: Examine:

CS CS Diplom Diplom: Major “ Major “Entwurf eingebetteter Systeme Entwurf eingebetteter Systeme” CS CS Diplom Diplom: Major Major Entwurf eingebetteter Systeme Entwurf eingebetteter Systeme CS/EE Master: CS/EE Master: Details pending… Details pending…

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

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ESII: Intro and Overview

The World of Embedded Systems y

Automotives

ABC, ABS, CBC, ESC DSC ECUs

Consumer Office Automation

ESC, DSC, ECUs,

Consumer

BlueRay DVD, Mobile phones, PDAs, MP3 players, Camera, Video Games

Office Automation

Printer, Fax, Copier, Scanner, Storage, point of sales terminals

Telecom/Military

Satellite, Radar, Sonar,

Automation

Building automation, , , , Flight control, Routers, Switches, Gateways, smart cameras g , heating, ventilation, air- conditioning, home automation, utility meter

Security

Surveillance, screening, sensors alarms

Medical/Healthcare

Hearing aids, MRI, pace makers micro robots

Clothing Environment

sensors, alarms makers, micro robots

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Test/Measurement

Ampere/Volt-meter, Logic Analyzer

g

E-/ Nano-tube textiles Sensor Networks

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ESII: Intro and Overview

Example 1 for an HD Video Codec Example 1 for an HD Video Codec for Mobile Applications

System System-

• On

On-

• a-
• Chip: CPU, Media

Chip: CPU, Media RAM, Video Codec IP, I/O RAM, Video Codec IP, I/O Silicon Technology: Silicon Technology: Silicon Technology: Silicon Technology: process: 65nm 65nm 22nm 22nm >> 1 billion > 1 billion

Other IPs

Peripheral 22nm 22nm >> 1 billion > 1 billion transistors/chip possible transistors/chip possible Practice: embedded systems Practice: embedded systems

• ften < 300million transistors
• ften < 300million transistors

H 264 CPU

• ften < 300million transistors
• ften < 300million transistors

Intel six Intel six-

• core Xeon

core Xeon 1.17 1.17 billion transistors billion transistors

H.264 Video Codec Media RAM

why ? why ?

• > “productivity gap”

> “productivity gap”

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source:Kimura@Renesas Tech.)

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ESII: Intro and Overview

Example 2 for a Quad-HD 3D-Video Example 2 for a Quad HD 3D Video Encoding for Multimedia 3D-TVs

3D 3D-

• Videos

Videos immense immense processing processing and and memory memory requirements requirements requirements requirements 82.4 TOPS, 54.6 TB/sec 82.4 TOPS, 54.6 TB/sec 6.4GB/s supported by 6.4GB/s supported by pp y pp y DDR2 DDR2-

• 800 at 100%

800 at 100% utilization utilization ASIC: Caches, memory, video ASIC: Caches, memory, video ASIC: Caches, memory, video ASIC: Caches, memory, video accelerators accelerators Silicon Technology: 90nm Silicon Technology: 90nm Issues Issues: Power, : Power, configurability configurability!!! !!! Design time: Design time: time time-

• to

to-market market

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source:Ding@ISSCC'09)

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ESII: Intro and Overview

Example 3a: E-Textiles - Smart Shirt Example 3a: E Textiles Smart Shirt

Nanotube textiles Cotton Cotton thread thread Cotto Cotto t ead t ead wrapped wrapped with with carbon carbon nanotubes nanotubes Light Light-weight weight

Source: Bourzac@TechnologyReview 2008

Light Light weight weight

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Source: [Marc03]

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ESII: Intro and Overview

Example 3b: E-Textile Example 3b: E Textile

eTextiles eTextiles Transceiver for Body Transceiver for Body eTextiles eTextiles Transceiver for Body Transceiver for Body Area Networks with remote Area Networks with remote Battery Power Battery Power 110 110 uW uW 110 110 uW uW 10 Mb/s 10 Mb/s ASIC: accelerators ASIC: accelerators ASIC: accelerators ASIC: accelerators Silicon Technology: 180nm, 0.9V Silicon Technology: 180nm, 0.9V

Source: [Patrick Mercier June 2009]

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Source: [Patrick Mercier, June 2009]

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ESII: Intro and Overview

Example 4: Medical Diagnostics Example 4: Medical Diagnostics

Madsen DTU) (source: J. Hesse: Medical Design’10@ Intel Embedded Community) source: Jan M

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(s (source: M. Kanaujia@Medgear’07)

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ESII: Intro and Overview

Example 5: Sensor Networks Example 5: Sensor Networks

Manufacturing plants & Power distribution

• Improve reliability, operating efficiency

Energy-efficient buildings

• $55 B / year
• pportunity in the

Disaster Prevention & Emergency Response

• pportunity in the

US Health care

• Unwired operating

rooms

• Early detection of

cardiac attacks Traffic control

• Reduce commute time

by 15 min => $15B/year “Smart” environments

• Homes, Offices, Schools, …
• Convenience, Productivity, Security
• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu cardiac attacks y $ y in California alone

(source: A. Raghunathan, NEC)

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ESII: Intro and Overview

What is an Embedded System? What is an Embedded System?

There is no concise definition of an embedded system There is no concise definition of an embedded system But here are some common characteristics … But here are some common characteristics …

specialized specialized to an application domain, single application or specific task (=> to an application domain, single application or specific task (=> less flexible but probably more efficiently to design) less flexible but probably more efficiently to design) Underlies many and Underlies many and tight constraints tight constraints (later) (later) Designing Designing an embedded system is typically more an embedded system is typically more challenging challenging than than designing a general designing a general-

• purpose computer

purpose computer Interacts with the real world Interacts with the real world => designing embedded software requires the => designing embedded software requires the Interacts with the real world Interacts with the real world => designing embedded software requires the => designing embedded software requires the consideration of more constraints than designing software for general consideration of more constraints than designing software for general-

• purpose computers

purpose computers By far By far higher volume higher volume than general than general-

• purpose computers. Example: a single

purpose computers. Example: a single l h l d 100 b dd d t l h l d 100 b dd d t luxury car has already >100 embedded systems luxury car has already >100 embedded systems Market revenue Market revenue for ES is by far higher than it is for general for ES is by far higher than it is for general-

• purpose

purpose computers (billions instead of millions) computers (billions instead of millions) New application areas evolve each day New application areas evolve each day New application areas evolve each day … New application areas evolve each day …

By exploiting the specific characteristics and by limitation to the known By exploiting the specific characteristics and by limitation to the known requirements an ES can be designed more efficiently => no requirements an ES can be designed more efficiently => no unnecessary overhead unnecessary overhead

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

unnecessary overhead unnecessary overhead

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ESII: Intro and Overview

Characteristics of Embedded Systems C a acte st cs o bedded Syste s

Efficient Efficient

Power/ Power/Energy Energy efficient efficient Power/ Power/Energy Energy efficient efficient Performance Performance efficient efficient Area Area efficient efficient Cost Cost efficient efficient

Dependable Dependable

• f

f Reliability Reliability probability probability of

• f correct

correct system system functioning functioning, , given given it it was was functional functional at time t=0 at time t=0 Availability Availability probability probability of

• f system

system in in function function at a at a given given time time t Maintainability Maintainability how much effort is it to operate/repair the system? how much effort is it to operate/repair the system? probability probability of

• f correct

correct system system functioning functioning after after encountering encountering an an error error error error Security Security retains retains confidentiality confidentiality Safety Safety causes causes no no harms harms

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: Lothar Thiele, ETH)

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ESII: Intro and Overview

Characteristics of Embedded Systems C a acte st cs o bedded Syste s

System System Constraints Constraints

D i D i M t i M t i Design Design Metric Metric Soft real Soft real-

• time

time constraints constraints results results in a Quality in a Quality-

• of
• f-Service (QOS)

Service (QOS) degradaation degradaation For For example example, a , a video video with with frame frame drops drops, 20 , 20 fps fps instead instead of 30

• f 30 fps

fps Hard real Hard real-

• time

time constraints constraints failure failure in in meeting meeting a a constraint constraint results results in in a a catastrophe catastrophe [Kopetz'97] [Kopetz'97] or

• r the

the result result is is no no more more useful useful p [ p 9 ] [ p 9 ]

System System Behavior Behavior

Reactive Reactive System System Reacts continuously to events in the physical Reacts continuously to events in the physical y y p y y p y world world Connected Connected to to the the physical physical world world via via sensors sensors, , for for instance instance

S t S t C iti C iti System System Composition Composition

Hybrid System Hybrid System composed composed of

• f both

both analog and digital analog and digital components components For For example example, a , a typical typical Digital Signal Digital Signal Processing Processing System System is is composed composed

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

p , yp yp g g g g g y p

• f an ADC, Digital Filters, DAC
• f an ADC, Digital Filters, DAC optional analog
• ptional analog amplifiers

amplifiers

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ESII: Intro and Overview

Moore’s Law Moore s Law

Gordon E. Moore (co Gordon E. Moore (co-

• founded Intel in 1968)

founded Intel in 1968)

tel)

Prediction in 1965: Prediction in 1965:

Exponential growth of number of transistors per Exponential growth of number of transistors per chip chip

(source: Int

chip chip Initial observation: Complexity per die area will Initial observation: Complexity per die area will double about every year double about every year Was later relaxed to “doubling every 18 months” Was later relaxed to “doubling every 18 months”

• Jan. 1971: Intel's

4004 chip; 2,200 transistors; a 4-bit microprocessor; it addressed 9.2 K of

Was later relaxed to “doubling every 18 months” Was later relaxed to “doubling every 18 months” This trend will continue for foreseeable future This trend will continue for foreseeable future Original paper: Original paper: “Cramming more components onto integrated circuits”, Electronics Volume 38 Number 8 April 19 1965

memory

Electronics, Volume 38, Number 8, April 19, 1965

2003: 2003: “ “No exponential is forever … but we can delay ‘FOREVER’ No exponential is forever … but we can delay ‘FOREVER’ ”, talk ”, talk by G. E. Moore at International Solid State Circuits Conference by G. E. Moore at International Solid State Circuits Conference (ISSCC), Feb. 2003. (ISSCC), Feb. 2003. For more info: International Technology Roadmap for Semiconductors: For more info: International Technology Roadmap for Semiconductors: http://public.itrs.net http://public.itrs.net

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

http://public.itrs.net http://public.itrs.net

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ESII: Intro and Overview

Visualization of Moore’s Law Visualization of Moore s Law

1970: 1k DRAM (introduced by Intel) 1970: 1k DRAM (introduced by Intel) 2005: 4G DRAM (150nm) 2005: 4G DRAM (150nm)

Factor 2^22 Factor 2^22 i.e., 4 million i.e., 4 million

2010: 64G DRAM (80nm) 2010: 64G DRAM (80nm)

2010 2010 1970 1970 fi ld fi ld 2010 2010 less than SIM card size less than SIM card size soccer field soccer field size size

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Note: exponential growth is larger than many people conceive! Note: exponential growth is larger than many people conceive!

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ESII: Intro and Overview

Memory: Functions/Chip and Average “M ’ L ” d Chi Si T d “Moore’s Law” and Chip Size Trends

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

16

ESII: Intro and Overview

Hard Disks and Moore's Law Hard Disks and Moore s Law

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: Hankwang’08)

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ESII: Intro and Overview

MPU: Functions/Chip and Average “M ’ L ” d Chi Si T d “Moore’s Law” and Chip Size Trends

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: ITRS@2009)

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ESII: Intro and Overview

Moore's Law and Intel Moore s Law and Intel

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: Intel)

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ESII: Intro and Overview

Memory Challenge Memory Challenge

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: IDF)

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ESII: Intro and Overview

Design Productivity Gap Design Productivity Gap

Transistors / Chip (w/o memory) Transistors / Staff-month

10000000 100000000

Gap

10000000

1000000 10000000

Limit to adding more skilled Engineers

100000

100000

Moore’s Law

1000 10000

1000

100 1981 1985 1989 1993 1997 2001 2005 2009

10

Engineering Productivity Trend

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

1981 1985 1989 1993 1997 2001 2005 2009

(source: [KeBri98]

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ESII: Intro and Overview

Trends: Crisis of Complexity

ESL: Elelctronic System-Level Design

Trends: Crisis of Complexity

Prediction for the case no

300

Millions of Gates

ESLTools will be used (blue graph) However: red graph may l d l d t S C ith

200 250

Available Gates Used Gates

apply and lead to SoCs with 100s –1000s of PEs per chip

100 150 200

Design Productivity Gap

55 50 47 43 32 25 20 10 8 3 2 1 0.8 0.4 0.3 0.2

50 100

1990 1992 1994 1996 1998 2000 2002 2004 2006

[source: Gartner/Dataquest]

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

[source: Gartner/Dataquest]

22

ESII: Intro and Overview

ITRS: Design Productivity Gap ITRS: Design Productivity Gap

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: ITRS@2007, Wolfgang Ecker @Infineon @DATE 2007)

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ESII: Intro and Overview

Shannon’s Law, Moore’s Law etc. Shannon s Law, Moore s Law etc.

Algorithmic Complexity

(src: A. Cuomo, ST Micro, Stockholm, Sept.8, 2004)

1000000 10000000

Algorithmic Complexity (Shannon’s Law) 4G

100000 1000000

Processor Performance 3G

1000 10000

(Moore’s Law) 2G

10 100

Battery Capacity

1 10

Battery Capacity 1G

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

24

ESII: Intro and Overview

Design Metrics Design Metrics

Performance Performance often the most prominent metric

• ften the most prominent metric

P ti P ti Power consumption Power consumption important for mobile battery

important for mobile battery-

• driven devices

driven devices

Reliability Reliability how reliable is the design under changing environmental and

how reliable is the design under changing environmental and

• perating conditions over time?
• perating conditions over time?
• perating conditions over time?
• perating conditions over time?

Peak Peak Temperature Temperature Size Size (transistor count chip area code size)

(transistor count chip area code size)

Size Size (transistor count, chip area, code size)

(transistor count, chip area, code size)

Cost per unit Cost per unit NRE cost: non NRE cost: non-recurring engineering costs recurring engineering costs NRE cost: non NRE cost: non recurring engineering costs recurring engineering costs Flexibility Flexibility how much effort is it to update/modify the design?

how much effort is it to update/modify the design?

Testability Testability can the system be tested with reasonable effort?

can the system be tested with reasonable effort?

Testability Testability can the system be tested with reasonable effort?

can the system be tested with reasonable effort?

Maintainability Maintainability how much effort is it to operate/repair the system?

how much effort is it to operate/repair the system?

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

…

25

ESII: Intro and Overview

Performance Performance

There are many definitions for performance … There are many definitions for performance … Speedup Speedup

Speedup of processor ‘A’ over ‘B’. S = Speedup of processor ‘A’ over ‘B’. S = throughput_A throughput_A / / throughput_B throughput_B

Throughput Throughput Throughput Throughput

In a pipeline: rate at which data is produced (maximum: 1/ In a pipeline: rate at which data is produced (maximum: 1/T_cyc T_cyc) ) Throughput of a system can be increased through concurrency Throughput of a system can be increased through concurrency

Latency Latency Latency Latency

Time it takes to produce a result (‘response time’) Time it takes to produce a result (‘response time’) Circuit latency: Example: time to execute a sequence of instructions Circuit latency: Example: time to execute a sequence of instructions (measured in # clock cycles) (measured in # clock cycles) (measured in # clock cycles) (measured in # clock cycles)

Cycle Time Cycle Time

Sequential logic: fastest clock that can be applied to a circuit determines Sequential logic: fastest clock that can be applied to a circuit determines the cycle time the cycle time T cyc T cyc the cycle time the cycle time T_cyc T_cyc

Propagation Delay Propagation Delay

Combinational logic: I/O propagation delay Combinational logic: I/O propagation delay

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

26

ESII: Intro and Overview

Power Consumption Power Consumption

Many embedded systems are Many embedded systems are battery battery-driven; some of them cannot driven; some of them cannot y ; be recharged for entire life time be recharged for entire life time Power efficiency is an important Power efficiency is an important characteristic: e g MHz/mW (see characteristic: e g MHz/mW (see

rrent [A] Energy ~ S I(t) dt != const

characteristic: e.g. MHz/mW (see characteristic: e.g. MHz/mW (see data sheets of embedded data sheets of embedded processors) processors) P i b dd d P i b dd d

cur

Power consumers in an embedded Power consumers in an embedded system system

Hardware: CPU, memory hierarchy Hardware: CPU, memory hierarchy ( i h t h ( i h t h

E l f l d Time T_a T_b

(main memory, caches, scratch (main memory, caches, scratch pad), communication (buses etc) pad), communication (buses etc) Software: application program, RTOS, … Software: application program, RTOS, …

Example for an evenly and unevenly discharged battery: the total capacity of the battery might vary = > can be exploited by power saving strategies

Peripherals: sensors, actuators, … Peripherals: sensors, actuators, …

Power Optimization strategies (at design time and/or operating time) Power Optimization strategies (at design time and/or operating time) Sili t h l th i i Sili t h l th i i hit t RTOS hit t RTOS

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Silicon technology, synthesis, micro Silicon technology, synthesis, micro-

• architecture, RTOS, power

architecture, RTOS, power management, compiler, algorithms, … management, compiler, algorithms, …

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ESII: Intro and Overview

Product life cycle for i d t semiconductors

Peak volume revenue Time (typically years) M k t t ( yp y y ) Market entry Product life cycle

Each generation marks a new silicon technology Each generation marks a new silicon technology Life cycles are overlapping Life cycles are overlapping Life cycles are overlapping Life cycles are overlapping Area under a curve refers to total Area under a curve refers to total generated revenue for a chip/device generation generated revenue for a chip/device generation

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

generated revenue for a chip/device generation generated revenue for a chip/device generation

28

ESII: Intro and Overview

Technology Production “Ramp” Curve ec

• ogy
• duct o

a p Cu e

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: ITRS@2009)

29

ESII: Intro and Overview

Time to Market Time to Market

Time to market: from idea to product Time to market: from idea to product Time to market is key: Time to market is key:

Delayed time to market significantly reduces revenue Delayed time to market significantly reduces revenue (might (might d l i f t) d l i f t) produce losses in fact) produce losses in fact) In some cases: if market entry is too early: market might not be In some cases: if market entry is too early: market might not be ready for product ready for product reduced peak volume reduced peak volume

enue Company A

reduced peak volume reduced peak volume significantly smaller significantly smaller total revenue total revenue

reve Company B Time (typically years)

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Delayed market entry

30

ESII: Intro and Overview

Cost Cost

NRE NRE cost cost NRE NRE cost cost

N Non

• n-
• Reccurring

eccurring Engineering cost: one ngineering cost: one-

• time cost of a new product

time cost of a new product (e.g. R&D etc) (e.g. R&D etc) R tl NRE t f t d b R tl NRE t f t d b i t h l i i t h l i Recently, NRE cost of newest deep sub Recently, NRE cost of newest deep sub-micron technologies micron technologies (65nm, 40nm, 22nm, and beyond) became very large (65nm, 40nm, 22nm, and beyond) became very large ⇒Volume needs to be very high (probably > 1 million) to amortize Volume needs to be very high (probably > 1 million) to amortize t costs costs This trend has a significant impact on the design of embedded This trend has a significant impact on the design of embedded systems (e.g. decreasing number of ASIC design starts) systems (e.g. decreasing number of ASIC design starts)

Cost per unit Cost per unit

Cost_unit Cost_unit = ( = (NRE_cost NRE_cost + #units * + #units * cost_of_one_unit cost_of_one_unit) / #units ) / #units The sales price should be higher than the cost of a unit The sales price should be higher than the cost of a unit The sales price will be determined by the market (e.g. competitors) The sales price will be determined by the market (e.g. competitors)

• J. Henkel, M. Shafique, KIT, WS1011

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31

ESII: Intro and Overview

Cost (cont’d) Cost (cont d)

0 35

Fab cost: $3 5bn

0.25 0.3 0.35 cron]

Fab cost: >$4bn Fab cost: ~$3.5bn design cyc: 8-10mo complex.: 4-6M apps: IAs,

• anyth. portable

Fab cost: ~$1 5bn

Intel 22nm Fab cost >$8Billion

0.15 0.2 0.25 nology [mic

Fab cost: >$4bn design cyc: 6-8mo complex.: 10-25M apps: ? Fab cost: ~$1.5bn design cyc: 12-18mo complex.: 200-500k apps: cell ph, PDAs, DVD, etc

$

0.05 0.1 Techn

Fab cost: ~$2.5bn design cyc: 10-12mo complex.: 1-2M apps: set-top box,

1997 1998 1999 2002 technology

wireless PDA

2002 technology 0.35 0.25 0.18 0.13 1997 1998 1999 2002

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

gy

32

ESII: Intro and Overview

NRE cost and volume NRE cost and volume

Varying NRE costs due to: Varying NRE costs due to:

Different silicon technology Different silicon technology Different silicon technology Different silicon technology Longer design time (e.g. time to refine the design) Longer design time (e.g. time to refine the design) Deployed design tools Deployed design tools …

Higher NRE cost may result in lower cost per produced unit Higher NRE cost may result in lower cost per produced unit Total cost depend on volume Total cost depend on volume

400000 500000 600000

NRE = 200,000; unit costs = 100 NRE = 50,000; unit cost = 500 NRE = 10 000; unit cost = 1 000

200000 300000 400000 total cost

NRE = 10,000; unit cost = 1,000

100000 50 100 150 200 250 300 350 400 450 500

• J. Henkel, M. Shafique, KIT, WS1011

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50 100 150 200 250 300 350 400 450 500 in 1000 units

33

ESII: Intro and Overview

Chip area Chip area

Chip area is not the major design constraint any more Chip area is not the major design constraint any more At the end of this decade it will be possible to integrate At the end of this decade it will be possible to integrate more than 3 billion (3x10^9) transistors on a single piece of more than 3 billion (3x10^9) transistors on a single piece of silicon silicon Oft ti Oft ti t k t i th t t i t th t hi i k t i th t t i t th t hi i Often, time Often, time-

• to

to-

• market is that stringent that chip area is

market is that stringent that chip area is sacrificed (trade sacrificed (trade-

• off)
• ff)

Chip complexity is often measured in gate equivalents: Chip complexity is often measured in gate equivalents: Chip complexity is often measured in gate equivalents: Chip complexity is often measured in gate equivalents:

⇒ the basic unit of measure of a digital logic circuit complexity. the basic unit of measure of a digital logic circuit complexity. Gate equivalent is the number of individual logic gates that Gate equivalent is the number of individual logic gates that would have to be connected to perform the same function would have to be connected to perform the same function would have to be connected to perform the same function would have to be connected to perform the same function

• J. Henkel, M. Shafique, KIT, WS1011

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34

ESII: Intro and Overview

Peak Temperature & Power Distribution ea e pe atu e &

• e

st but o

Peak Temperature Peak Temperature Cooling Cost Cooling Cost

(src: B. Holt@Intel, 2005)

p g Hot Spot Mitigation Hot Spot Mitigation Holistic System Level Optimization Holistic System Level Optimization

• J. Henkel, M. Shafique, KIT, WS1011

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Holistic System Level Optimization Holistic System Level Optimization Reduced Reduced thermal thermal resistance resistance, , Airflow Airflow, Layout , Layout enhancements enhancements

35

ESII: Intro and Overview

Reliability: Soft Errors Reliability: Soft Errors

SEU Si l E t U t MEU M lti l E t U t SEU: Single Event Upset

Single-Bit Upsets Multiple-Bit Upsets

MEU: Multiple Event Upset

Several SEUs occurring simultaneously Multiple Bit Upsets y High Integration increases MEUs Single-Bit Upsets at multiple locs. Multiple Bit Upsets at multiple locs Multiple-Bit Upsets at multiple locs.

• R. Baumann (TI)

Design&Test05

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

36

ESII: Intro and Overview

Interdependency of design metrics Interdependency of design metrics

temp. reliability chip size power y

Constraints may by Constraints may by contradictory contradictory

Example: high performance Example: high performance i l t t t h l d i l t t t h l d perf cost

bus1 bus2

requires latest technology and requires latest technology and thus will be quite expensive thus will be quite expensive

A real A real-

• world solution is always a

world solution is always a compromise compromise between various between various

pe cost DSP

ASIC1

compromise compromise between various between various design constraints design constraints It is an art to weigh various It is an art to weigh various constraints against each other constraints against each other

CPU

ASIC2 bus3

constraints against each other constraints against each other and to find the best compromise and to find the best compromise between all possible solutions between all possible solutions (I.e. design space) (I.e. design space)

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu bus3

( g p ) ( g p )

37

ESII: Intro and Overview

Columns of Embedded System Design

• 1. Embedded processor
• 1. Embedded processor Architectures

Architectures

General General-

• purpose computer architectures are hardly appropriate for

purpose computer architectures are hardly appropriate for ES since they offer a fair compromise between many constraints ES since they offer a fair compromise between many constraints y p y y p y but they do not allow to adapt to the specific needs for ES but they do not allow to adapt to the specific needs for ES

• 2. Electronic System
• 2. Electronic System-
• Level design

Level design (ESL) methodologies (ESL) methodologies

Raising complexity of systems Raising complexity of systems on

• n chip (SOC) requires design

chip (SOC) requires design Raising complexity of systems Raising complexity of systems-on

• n-chip (SOC) requires design

chip (SOC) requires design methodologies at higher level of abstraction methodologies at higher level of abstraction The large design space to be efficiently explored The large design space to be efficiently explored

• 3. Embedded
• 3. Embedded Software

Software

Software engineering: MDA Model Software engineering: MDA Model-

• Driven Architecture, ...

Driven Architecture, ...

4 Technology Technology of integrated circuits

• f integrated circuits

4.

• 4. Technology

Technology of integrated circuits

• f integrated circuits

New technologies offer new possibilities for ES design New technologies offer new possibilities for ES design Example: reconfigurable computing due to advances in FPGA Example: reconfigurable computing due to advances in FPGA technology technology

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

technology technology

38

ESII: Intro and Overview

• 1. Architectures
• 1. Architectures

…

“Hardware solution”

ASI Cs

ps/area,

ASI Cs

• Non-programmable,
• highly specialized

Reconfigurable C ti

“System Requirement”

mW, Mip

MPSoCs

• DSP+ ASIC+ ASIP

,

Computing

• adaptive,
• hardware accelerators

/$, MHz/

ASI Ps

ISA extension

• Design-time

selection cy: Mips/

“Software l ti ”

DSPs

• programmable
• ISA extension,
• parameterization

Efficienc

solution”

• programmable,
• DSP/VLIW ISA

GPPs

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Flexibility, 1/time-to-market, …

39

ESII: Intro and Overview

General-purpose Processor General purpose Processor

Features Features

Fully programmable Fully programmable General General p rpose p rpose

Data path Control path

General General-purpose purpose ALU, FPU etc ALU, FPU etc For ‘any’ application For ‘any’ application

Control logic S tate registers R egister file AL U , FP U

General General-

• purpose

purpose instruction set instruction set Non Non-

• extensible

extensible

General-purpose S tate registers P C IR R egister file

High SW flexibility High SW flexibility Un Un-

• expensive

expensive

• General purpose

P rocessor P rogram Data

…

P rogram memory Data memory

• J. Henkel, M. Shafique, KIT, WS1011

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40

ESII: Intro and Overview

Very-Long Instruction Word (VLIW) Very Long Instruction Word (VLIW)

Features Features

F ll bl F ll bl Fully programmable Fully programmable General General-

• purpose or

purpose or Specialized Specialized functional functional units units, , ALU, FPU, etc. ALU, FPU, etc. Multiple Multiple instructions instructions per per cycle cycle Mainly for Signal Mainly for Signal Processing applications Processing applications General General-purpose and purpose and General General purpose and purpose and Specialized instruction set Specialized instruction set Non Non-

• extensible

extensible High SW flexibility High SW flexibility High SW flexibility High SW flexibility Requires Requires sophisticated sophisticated compilers compilers

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: Philips Nexperia: VLIW White Paper)

…

41

ESII: Intro and Overview

ASIP, Extensible Processor ASIP, Extensible Processor

Data path Control path

Features Features

Fully Programmable Fully Programmable General p rpose or General p rpose or

Control logic AL U , FP U

General purpose or General purpose or specialized ALU, FPU, specialized ALU, FPU, Adapted to an Adapted to an li ti d i ( li ti d i (

S tate registers E xtensible

• additional

AL U’s etc.

application domain (e.g. application domain (e.g. multimedia) multimedia) Instruction may be Instruction may be

• E

xtensible instruction set

• special

registers R egister file

extensible extensible Good software flexibility Good software flexibility Relatively expensive Relatively expensive

P C IR AS IP , E xtensible P rocessor

e at e y e pe s e e at e y e pe s e since lower volume since lower volume

P rogram Data

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

memory memory

42

ESII: Intro and Overview

Reconfigurable Processors Reconfigurable Processors

Features Features

Programmable Programmable Functional Units (FUs) Functional Units (FUs) Functional Units (FUs) Functional Units (FUs) and Register Files and Register Files (RFs) (RFs) Adapted to different Adapted to different Adapted to different Adapted to different application domains application domains Communication Communication Multimedia Multimedia ... ... Require complex tools Require complex tools equ e co p e too s equ e co p e too s Relatively expensive Relatively expensive since lower volume since lower volume

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: ADRES)

43

ESII: Intro and Overview

Accelerator, ASIC Accelerator, ASIC

Features Features

A very specialized A very specialized ‘Processor” only for one ‘Processor” only for one

Data path Control path

Processor , only for one Processor , only for one application application Hardwired (no instruction set) Hardwired (no instruction set) V i b f V i b f

Control logic S tate registers R egister file AL U , FP U

Very expensive because of Very expensive because of high NRE cost (needs high high NRE cost (needs high volume) volume)

Accelerator (AS IC) S tate registers R egister file

Unsurpassed efficiency Unsurpassed efficiency Low power Low power High performance High performance

Accelerator (AS IC) Data

g pe o a ce g pe o a ce …

Data memory

• J. Henkel, M. Shafique, KIT, WS1011

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44

ESII: Intro and Overview

• 2. ESL Design Methodology
• 2. ESL Design Methodology

Wh t? Wh t? > ESL El t i S t > ESL El t i S t l l d i l l d i What? What? -

• > ESL: Electronic System

> ESL: Electronic System-

• level design

level design

(Co) (Co)-

• Synthesis, (co)

Synthesis, (co)-

• simulation, verification, …

simulation, verification, … Design a whole system rather than single un Design a whole system rather than single un-

• adapted components

adapted components

Why? Why?

Complexity of future embedded systems may not be handled (‘gap’) Complexity of future embedded systems may not be handled (‘gap’) Optimize with system component interdependencies in mind Optimize with system component interdependencies in mind Optimize with system component interdependencies in mind Optimize with system component interdependencies in mind

How? How?

Need to raise the abstraction level: Functionality rather than Need to raise the abstraction level: Functionality rather than i l t ti (i HW SW fi ) i l t ti (i HW SW fi ) implementation (i.e. HW, SW, firmware) implementation (i.e. HW, SW, firmware)

Benefits? Benefits?

Fast design space exploration Fast design space exploration g p p g p p Allows to build complex designs and thus to make use of available silicon Allows to build complex designs and thus to make use of available silicon technology technology

• J. Henkel, M. Shafique, KIT, WS1011

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45

ESII: Intro and Overview

Co-Design of hardware and software Co Design of hardware and software

Hardware and Hardware and software are no longer software are no longer developed separately developed separately

Compilers (1960's 1970's) Behavioral synthesis (1990's) Sequential program code (e.g., C, VHDL)

developed separately developed separately Basic techniques in Basic techniques in SW and HW are SW and HW are

Assembly instructions Register transfers (1960 s,1970 s) A bl li k RT synthesis (1980's, 1990's)

SW and HW are SW and HW are matured and can be matured and can be used to concurrently used to concurrently d i h d d d i h d d

Machine instructions Assemblers, linkers (1950's, 1960's) Logic synthesis (1970's, 1980's) L i t Logic equations / FSM's

design hardware and design hardware and software software

=> hardware/software co => hardware/software co-

Implementation Microprocessor plus bit “ ft ” VLSI, ASIC, or PLD i l t ti “h d ” Logic gates

hardware/software co hardware/software co design design

program bits: software implementation: “hardware”

The “co-design ladder” by F. Vahid

• J. Henkel, M. Shafique, KIT, WS1011

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46

ESII: Intro and Overview

Design Methodology Design Methodology

Abstraction level Synthesis IP

d software System Spec System synthesis Platforms (SW. HW, OS, firmware)

Synthesis

rdware and Behavioral Spec Behav Synthesis OS, firmware) IP cores y Har Behavioral Spec

• Behav. Synthesis

IP cores rdware only Register-transfer (RT) Spec RT synthesis RT components Har Logic Spec Logic Synthesis gates

• J. Henkel, M. Shafique, KIT, WS1011

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47

ESII: Intro and Overview

ESL Design Methodology E l MPEG 2 id E d Example: MPEG-2 video Encoder

CPU1 CPU2 DSP1 CPU1 CPU1 CPU2 CPU2 DSP1 DSP1 CPU1 CPU1 Communication: Communication: (b (b hi t k) hi t k) CPU2 CPU2 DSP1 DSP1 CPU1 CPU1 CPU1 CPU1 Communication: Communication: (b (b hi t k) hi t k) Communication: Communication: (b (b hi t k) hi t k) CPU2 CPU2 CPU2 CPU2 DSP1 DSP1 DSP1 DSP1 Main Memory Main Memory (buses, on (buses, on-

• chip network)

chip network) Caches Caches I/O I/O Main Memory Main Memory Main Memory Main Memory (buses, on (buses, on-

• chip network)

chip network) (buses, on (buses, on-

• chip network)

chip network) Caches Caches Caches Caches I/O I/O I/O I/O

A simple architecture ESL Design Flow

( [H k l/Li’02])

MPEG-2 video encoder

Software I cache

90 ntage ( %)

Power/ performance Breakdown

(source: [Henkel/Li’02])

I-cache D-cache Memory

50 10 Energy percen

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Instruction cache size (2x) 10 E

48

ESII: Intro and Overview

• 3. Embedded Software
• 3. Embedded Software

“Classical Software” “Classical Software” Classical Software Classical Software

Software is the realization of mathematical functions as procedures Software is the realization of mathematical functions as procedures A set of input data is mapped into a set of output data A set of input data is mapped into a set of output data The mechanism that executes the procedures is not as important The mechanism that executes the procedures is not as important as the abstract properties of the functions as the abstract properties of the functions In theory, the mechanism can be implemented by a Turing In theory, the mechanism can be implemented by a Turing y p y g y p y g machine machine See also [Lee01] See also [Lee01]

Embedded Software is different: Embedded Software is different:

Interaction ith the real

• rld is most important

Interaction ith the real

• rld is most important

Interaction with the real world is most important Interaction with the real world is most important

• J. Henkel, M. Shafique, KIT, WS1011

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49

ESII: Intro and Overview

Embedded Software Properties Embedded Software Properties

Example: a software of an Anti Example: a software of an Anti-

• lock Braking System, ABS,

lock Braking System, ABS, in a car in a car The ABS software should be able to: The ABS software should be able to:

react to driver pushing the brake pad => react to driver pushing the brake pad => REACTIVITY REACTIVITY stop the car before hitting the tree stop the car before hitting the tree -

• >

> TIMELINESS TIMELINESS monitor wheel RPM while actuating brakes => monitor wheel RPM while actuating brakes => CONCURRENCY CONCURRENCY handle the next situation after having completed the current one handle the next situation after having completed the current one handle the next situation after having completed the current one handle the next situation after having completed the current one => => LIVENESS LIVENESS …

CBC

(src: www bmw co nz)

CBC: Cornering Brake Control

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: www.bmw.co.nz)

50

ESII: Intro and Overview

Embedded Software (cont’d) Embedded Software (cont d)

Timeliness Timeliness

C t ti d t k ti d t b id d h d i C t ti d t k ti d t b id d h d i Computation does take time; needs to be considered when design Computation does take time; needs to be considered when design ES ES

Concurrency Concurrency

ES interacts typically with more than one physical process => must ES interacts typically with more than one physical process => must be able to react simultaneously be able to react simultaneously

Liveness Liveness Liveness Liveness

ES must not terminate or block waiting for events that won’t occur ES must not terminate or block waiting for events that won’t occur

Reactivity Reactivity eac y eac y

React continuously to events in the physical world React continuously to events in the physical world

Heterogeneity Heterogeneity

ES implementation is typically a mix of computational and ES implementation is typically a mix of computational and implementational implementational styles styles Heterogeneous event handling styles Heterogeneous event handling styles

• J. Henkel, M. Shafique, KIT, WS1011

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51

ESII: Intro and Overview

• 4. IC technologies
• 4. IC technologies

Standard-ICs Application-specific ICs hard-wired mask- programmable custom programmable application- specific ROM DRAM, SRAM,… semi- c stom full- c stom uP standard System , PROM, EPROM PLD, EPLD custom custom Gate- Standard-/ PGAs uP, DSP, … components I/O, EPROM, EEPROM, … EPLD, EEPLD, … Array, Sea of Gates Macro Cells XILINX,

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Graphic, … Gates , Actel, …

52

ESII: Intro and Overview

Custom vs. Semicustom

Custom Custom

Functional and physical design are handcrafted Functional and physical design are handcrafted High potential for optimization High potential for optimization But: extensive effort But: extensive effort

S i S i t Semi Semi-custom custom

Restricting # of circuit primitives Restricting # of circuit primitives Smaller optimization potential Smaller optimization potential Smaller optimization potential Smaller optimization potential Focus is on interconnection of primitives Focus is on interconnection of primitives Restriction makes it easier to develop CAD tools Restriction makes it easier to develop CAD tools A l b f i l i h i b l d h h A l b f i l i h i b l d h h A larger number of implementation choices can be explored through A larger number of implementation choices can be explored through usage of efficient CAD tools usage of efficient CAD tools

Structured/Platform ASICs Structured/Platform ASICs Structured/Platform ASICs Structured/Platform ASICs

Falls between an FPGA and a Standard Cell Falls between an FPGA and a Standard Cell-

• based ASIC

based ASIC mid mid-

• volume level designs

volume level designs

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

map the circuit into a fixed arrangement of known cells map the circuit into a fixed arrangement of known cells

53

ESII: Intro and Overview

Semi-custom Design Styles Semi custom Design Styles

C ll b d A b d Cell-based Array-based Standard cells Macro cells Pre-diffused Pre-wired

Memory, PLA Gate Array, Sea of Gates Anti-fuse, PLA, … Sea of Gates, … …

• J. Henkel, M. Shafique, KIT, WS1011

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54

ESII: Intro and Overview

Semi-custom Design Styles (cont’d) Semi custom Design Styles (cont d)

Standard cells: Standard cells: From a library ( From a library (param param: technology, area, delay, voltage, …) : technology, area, delay, voltage, …) -

• >

> large large -

• > high maintenance

> high maintenance Macro cells (“building blocks”) Macro cells (“building blocks”) Module/cell generators: do placing + wiring when functional Module/cell generators: do placing + wiring when functional description is given description is given p g p g Exmpl Exmpl: PLAs ( : PLAs (Progr

• Progr. Logic Arrays)

. Logic Arrays) Compatibility w/ custom components (combining) like done in Compatibility w/ custom components (combining) like done in uP uP design design g Array Array-

• based

based Matrix of “ Matrix of “uncommited uncommited components”. They are personalized and components”. They are personalized and connected (i e FPGA) connected (i e FPGA) connected (i.e. FPGA) connected (i.e. FPGA) Technologies: mask programmable, field programmable Technologies: mask programmable, field programmable

• J. Henkel, M. Shafique, KIT, WS1011

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55

ESII: Intro and Overview

Factors Affecting an ASIC Development acto s ect g a S C e e op e t

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: Fuse Handbook On Best Practice in ASIC Development: ASIC Working Group: 1999)

56

ESII: Intro and Overview

Structured ASICs: Architecture

Two Main Levels Two Main Levels

Structured Elements Structured Elements Structured Elements Structured Elements

Combinational and sequential function Combinational and sequential function blocks blocks Can be a logical or storage element Can be a logical or storage element Can be a logical or storage element Can be a logical or storage element

Array of Structured Elements Array of Structured Elements

Uniform or non Uniform or non-

• uniform array styles

uniform array styles A fi d f d A fi d f d A fixed arrangement of structured A fixed arrangement of structured elements elements

Structured Elements Structured Elements Structured Elements Structured Elements

Fine Fine-

• Grained

Grained

unconnected discrete components unconnected discrete components transistors resistors etc transistors resistors etc transistors, resistors, etc. transistors, resistors, etc.

Medium Medium-

• Grained

Grained

gates, MUX’s, LUT’s or flip gates, MUX’s, LUT’s or flip-

• flops

flops

• J. Henkel, M. Shafique, KIT, WS1011

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Hierarchical Hierarchical

(src: STRUCTURED ASIC’s, Dan Lander)

57

ESII: Intro and Overview

Dies of semi-custom design styles Dies of semi custom design styles

specific Applic.-s cro cells using mac

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: DeMi94)

58

ESII: Intro and Overview

C i f i t t h Comparison of semi-custom techn.

C C ff Custom Cell-base Pre-diffused Pre-wired Density very high high high med-low Perform. very high high high med-low Flexibility very high high medium low Design Time very long short short very short

• Manuf. Time

medium medium short ver short Cost: low vol. very high high high low Cost: high vol. low low low high

• J. Henkel, M. Shafique, KIT, WS1011

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59

ESII: Intro and Overview

Sneak Preview

• 1. Introduction to Embedded Systems
• models of computation
• Spec languages

y 2, 3, 4, 5 SYSTEM SPECIFICATION Optimization

• low power, performance,

area, reliability, peak temp. …

Design Space Exploration

• low power, performance, area, reliability,…

refine

SYSTEM PARTITIONING Estimation&Simulation

• low power, performance,

area, reliability, peak temp. …

Embedded Processor Design & Architectures Embedded Software 7 ISA extensions 6 Code Middleware, RTOS 13 & 14 Hardware Design

• Synthesis

embedded IP:

• PEs
• 8. ASIPs, Extensible

P

• 7. ISA extensions

Special Instructions

• 6. Code

Generation for Embedded Systems 13 & 14. Scheduling

• Memories
• Communication
• Peripherals
• …

Processors Optimize for

• Low Power
• Performance
• 9. DSPs, VLIW

10 & 11 R fi bl

• Integration
• Prototyping
• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu IC technology

• Area
• Reliability

10 & 11. Reconfigurable Processors Prototyping

• Tape out
• 12. Multi-Corefuture

60

ESII: Intro and Overview

Applying Concepts to Real-World Applications

After each lecture: After each lecture: After each lecture: After each lecture: The concepts will be applied to a real The concepts will be applied to a real-

• world application from the

world application from the multimedia domain multimedia domain A video conferencing system with an advance video codec A video conferencing system with an advance video codec A video conferencing system with an advance video codec A video conferencing system with an advance video codec Optional Optional An application for student to practice their knowledge An application for student to practice their knowledge An application for student to practice their knowledge An application for student to practice their knowledge Suggested Suggested topics topics ( (Possibility Possibility of

• f self

self-

• choice

choice is is there there) ) Multimedia TV Multimedia TV Automotive Automotive Vision Vision based based Control Control System System Automotive Automotive Vision Vision-based based Control Control System System Recommendation Recommendation Groups Groups of 2

• f 2-
• 3

3 Peer Peer-

• Discussions

Discussions Benefits Benefits Benefits Benefits Strengthen the knowledge by applying concepts of design Strengthen the knowledge by applying concepts of design methodologies and methodologies and architectural architectural options

• ptions

Exploration of Exploration of future future interests interests Career Career-Orientation Orientation

• J. Henkel, M. Shafique, KIT, WS1011

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Exploration of Exploration of future future interests interests Career Career Orientation Orientation Exploration of relevant Exploration of relevant research research and and industrial industrial interests interests

61

ESII: Intro and Overview

Information on Exams and Slides Information on Exams and Slides

ID: student, PWD: CES ID: student, PWD: CES-

• Student

Student The The exam exam can can be be in German in German or

• r English

English

• J. Henkel, M. Shafique, KIT, WS1011

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62

ESII: Intro and Overview

Summary Summary

Embedded systems are ubiquitous Embedded systems are ubiquitous Future embedded systems will be of large complexity, low Future embedded systems will be of large complexity, low power, tiny sized, low cost, … (=> ambient) power, tiny sized, low cost, … (=> ambient) Key: ESL design methodologies, embedded software, Key: ESL design methodologies, embedded software, embedded architectures, IC technologies embedded architectures, IC technologies Th b d b t h d d ft i bl d HW Th b d b t h d d ft i bl d HW The border between hardware and software is blurred. HW The border between hardware and software is blurred. HW and SW are designed together (HW/SW co and SW are designed together (HW/SW co-

• design)

design) Embedded system’s designer Embedded system’s designer Embedded system s designer Embedded system s designer

Skills from two core groups are needed” Computer Science and Skills from two core groups are needed” Computer Science and Engineering Engineering Diversity is very high: design methodologies, architectures, Diversity is very high: design methodologies, architectures, compilers, IC technology, … compilers, IC technology, …

• J. Henkel, M. Shafique, KIT, WS1011

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63

ESII: Intro and Overview

References and Sources References and Sources

• [Lee01] E.A.Lee, “Embedded Software”, M. Selkowitz (Ed.) in Advances in Computers, Vol. 56,

Academic Press, London, 2002.

• [Marc03], Marculescu, D.; Marculescu, R.; Park, S.; Jayaraman, S.;

“Ready to ware”, Spectrum, IEEE ,Volume: 40 , Issue: 10 , Oct. 2003, Pages:28 - 32 Ready to ware , Spectrum, IEEE ,Volume: 40 , Issue: 10 , Oct. 2003, Pages:28 32

• [Vahid02] F. Vahid, T. Givargis, Embedded System Design, John Wiley&Sons, 2002.
• [HeLi02] Henkel, J.; Yanbing Li, “Avalanche: an environment for design space exploration and
• ptimization of low-power embedded systems, Very Large Scale Integration (VLSI) Systems, IEEE

Transactions on Volume: 10 Issue: 4 Aug 2002 Pages:454 468 Transactions on ,Volume: 10 , Issue: 4 , Aug. 2002, Pages:454 – 468

• Intel: www.intel.com
• ITRS: http://www.itrs.net/
• J. Henkel, M. Shafique, KIT, WS1011

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64

ESII: Intro and Overview

Extra Slides

Prof Dr J Henkel M Shafique Prof Dr J Henkel M Shafique

• Prof. Dr. J. Henkel, M. Shafique
• Prof. Dr. J. Henkel, M. Shafique

CES CES -

• Chair for Embedded Systems

Chair for Embedded Systems Karlsruhe Institute of Technology, Germany Karlsruhe Institute of Technology, Germany

Today: Introduction and Overview Today: Introduction and Overview

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

65

ESII: Intro and Overview

(source: Intel)

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

66

ESII: Intro and Overview

Complexity of Microprocessors Complexity of Microprocessors

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: Intel)

67

ESII: Intro and Overview

Transistor Count and Moore's Law Transistor Count and Moore s Law

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(compiled by: C. Kopp’05)

68

ESII: Intro and Overview

CPU Frequency and Moore's Law CPU Frequency and Moore s Law

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(compiled by: C. Kopp’05)

69

ESII: Intro and Overview

DRAM and Flash Memory Trends DRAM and Flash Memory Trends

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(source: ITRS@2009)

70

ESII: Intro and Overview

Computation Power vs. Moore's Law p

(source: J. G. Koomey’10: Outperforming Moore's Law

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

p g @IEEESpectrum)

71

ESII: Intro and Overview

Thermal Budget is Decreasing Thermal Budget is Decreasing

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: B. Holt@Intel, 2005)

72

ESII: Intro and Overview

Soft Error Tolerance and Evasion

Fault Confinement

Contain before Spread

Reconfiguration

Replace or reconfigure Contain before Spread Multiple Requests/Confirmation

Fault Detection

p g If transient permanent

Recovery

Error Detection and Correction Codes

F lt M ki

Resume operation after reconfiguration Degraded mode

Fault Masking

Redundancy and Majority Voting

Retry

Degraded mode

Restart

Re-initialize

Retry

Second Attempt for Transient problems

Repair

Defective component

Diagnosis

Figure out what went wrong

Reintegration

After repair

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

Before Detection Degraded Full Operation

73

ESII: Intro and Overview

ASIC Family Tree ASIC Family Tree

• J. Henkel, M. Shafique, KIT, WS1011

http://ces.itec.kit.edu

(src: Fuse Handbook On Best Practice in ASIC Development: ASIC Working Group: 1999)