Synthesizing an Instruction Selection Rule Library from Semantic - PowerPoint PPT Presentation

1 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD Programming Paradigms Chair, IPD Snelting Compiler Design Lab Synthesizing an Instruction Selection Rule Library from Semantic Specifjcations Sebastian Buchwald, Andreas Fried, Sebastian Hack KIT – The Research University in the Helmholtz Association www.kit.edu

Instruction Selection 1 Replace IR pattern with a single goal instruction 1 0 z y x andn %x, %y, %z 0 0 2 z y x Not And IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 No total ordering, no (virtual) register allocation yet

State of the Art 3 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD rule library instruction selector Syntactic specifjcation of patterns Code generation E.g. GCC machine description, LLVM TableGen Large rule libraries, growing larger Tedious manual maintenance Error-prone, especially missing patterns

Multiple Patterns per Goal Sub x y 0 1 0 1 And Xor y x 0 1 0 1 Full support of new instruction needs 4 rules + commutativity And 1 4 0 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD And Not x y 1 0 0 Xor Or x y 0 1 Easier to specify semantics once

Existing Rulesets are Incomplete movb (%p,%x,2), %r leal a+42(%x,%y,4), %r r = *(p + ( x + x ) )); r = &a[ 42 + x + 4*y]; …but susceptible to commutativity or associativity movb (%x,%p), %r addl $a+42, %z addl %x, %p leal (%x,%y,4), %z Rules are missing from GCC 7.3 (left) and Clang 6.0.0 (right) leal a+42(%x,%y,4), %r 5 r = *(p + x + x); r = &a[x + 4*y + 42]; x86 has extensive addressing modes IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 movb (%p,%x,2), %r = ⇒ = ⇒

Existing Rulesets are Incomplete movb (%p,%x,2), %r leal a+42(%x,%y,4), %r r = *(p + ( x + x ) )); r = &a[ 42 + x + 4*y]; …but susceptible to commutativity or associativity movb (%x,%p), %r addl $a+42, %z addl %x, %p leal (%x,%y,4), %z Rules are missing from GCC 7.3 (left) and Clang 6.0.0 (right) leal a+42(%x,%y,4), %r 5 r = *(p + x + x); r = &a[x + 4*y + 42]; x86 has extensive addressing modes IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 movb (%p,%x,2), %r = ⇒ = ⇒

Existing Rulesets are Incomplete movb (%p,%x,2), %r leal a+42(%x,%y,4), %r r = *(p + ( x + x ) )); r = &a[ 42 + x + 4*y]; …but susceptible to commutativity or associativity movb (%x,%p), %r addl $a+42, %z addl %x, %p leal (%x,%y,4), %z 5 Rules are missing from GCC 7.3 (left) and Clang 6.0.0 (right) leal a+42(%x,%y,4), %r r = *( ( p + x ) + x); r = &a[x + 4*y + 42 ]; x86 has extensive addressing modes IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 movb (%p,%x,2), %r = ⇒ = ⇒ = ⇒ = ⇒

New Approach instruction Correct and complete rule libraries Find all smallest IR patterns equivalent to g For each machine instruction g : Synthesize rule library Semantic specifjcation of instructions Synthesis selector library 6 rule specifjcation machine specifjcation IR IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 Push-button support for new ISAs or ISA extensions

Specifying Instructions andn 7 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD And Semantics Q relate arguments to results: Not Gulwani et al., PLDI 2011 Specifjcation as SMT terms: v a [ 0 ] v a [ 1 ] v a [ 0 ] v a [ 0 ] v a [ 1 ] v r [ 0 ] v r [ 0 ] v r [ 0 ] Arguments v a and results v r are 32-bit bitvectors Q And = ( v r [ 0 ] = v a [ 0 ] ∧ v a [ 1 ]) Q Not = ( v r [ 0 ] = ¬ v a [ 0 ]) Q andn = ( v r [ 0 ] = ¬ v a [ 0 ] ∧ v a [ 1 ])

Component-Based Synthesis 0 SMT solver fjnds connections with connections from Produce pattern semantics Q components SMT encoding of connections between machine instruction as goal Provide IR instructions as components, 1 1 Gulwani et al., PLDI 2011 0 y x Xor And IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 8 correct semantics

Component-Based Synthesis 0 SMT solver fjnds connections with connections from Produce pattern semantics Q components SMT encoding of connections between machine instruction as goal Provide IR instructions as components, 1 1 Gulwani et al., PLDI 2011 0 y x Xor And IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 8 correct semantics

Component-Based Synthesis Gulwani et al., PLDI 2011 correct semantics SMT solver fjnds connections with connections components SMT encoding of connections between machine instruction as goal Provide IR instructions as components, 1 0 1 0 y x Xor And IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 8 Produce pattern semantics Q + from Q + = Q Xor ([ a , b ] , [ c ]) ∧ Q And ([ d , e ] , [ f ]) ∧ ( a = x ) ∧ ( b = y ) ∧ ( d = c ) ∧ ( e = y ) ∧ ( result = f )

Component-Based Synthesis Gulwani et al., PLDI 2011 correct semantics SMT solver fjnds connections with connections components SMT encoding of connections between machine instruction as goal Provide IR instructions as components, 1 0 1 0 y x Xor And IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 8 Produce pattern semantics Q + from Q + = Q Xor ([ a , b ] , [ c ]) ∧ Q And ([ d , e ] , [ f ]) ∧ ( a = x ) ∧ ( b = y ) ∧ ( d = c ) ∧ ( e = y ) ∧ ( result = f )

Memory Access 9 IR graph includes memory dependencies (→ HotSpot) 2 1 0 x m addr addl %x, (%addr) 2 0 1 1 0 1 0 x m addr Load Add Store IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 Store: update, Load: query Actually use notional SSA value for memory state m : M

SMT Representation ( *addr + x ) 8 addr + 2 addr + 1 addr 31 ( *addr + x ) 24 23 ( *addr + x ) 16 15 7 10 ( *addr + x ) 0 Only model those Extract symbolic addresses from goal’s semantics But most addresses are irrelevant IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 addr + 3 Theory “ArraysEx” provides maps, M = Array ( Pointer , Value ) Problem: ∀ m : M . . . and ∄ m : M . . . : 2 2 35 possibilities

SMT Representation But most addresses are irrelevant 10 Only model those IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 Theory “ArraysEx” provides maps, M = Array ( Pointer , Value ) Problem: ∀ m : M . . . and ∄ m : M . . . : 2 2 35 possibilities ⇒ Extract symbolic addresses from goal’s semantics addr �→ ( *addr + x ) 0 ... 7 addr + 1 �→ ( *addr + x ) 8 ... 15 addr + 2 �→ ( *addr + x ) 16 ... 23 addr + 3 �→ ( *addr + x ) 24 ... 31

Synthesis Task 11 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD Unfortunately intractable as-is: Too many difgerent components Gulwani’s technique: Assumes right components already selected Enumeration: Search space too large ∃ p : Pattern . ∀ v a : Args . ∀ v r : Results . Q + ( p , v a , v r ) ⇐ ⇒ Q ( goal , v a , v r ) ∀ quantifjers ⇒ Counterexample-guided inductive synthesis (CEGIS) ⇒ Need a compromise

Iterative CEGIS Each pattern needs few, but some Run synthesis for each 12 Iterate over sub-multisets of IR in Solution: multiple times increasing size with extraneous components Gulwani’s algorithm has problems IPD Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection 2018-02-28 ∃ p : Pattern . ∀ v a : Args . ∀ v r : Results . Q + ( p , v a , v r ) ⇐ ⇒ Q ( goal , v a , v r ) IR = { Add , Load , Store } { Add } { Load } IRs provide > 20 instructions { Store } { Add , Add } { Add , Load } { Add , Store } { Load , Load } { Load , Store } { Store , Store } { Add , Add , Add } { Add , Add , Load } …

Synthesis Results 10:27:06 70 2106 7 18:10:58 Binary arithmetic 260 6316 6 cmp / test; jcc 5:45 265 145441 7 3:00:07:05 Total 630 154470 7 Unary arithmetic 4 13 #Goals 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD IR: 22 simple operations Machine instructions: IA32 32-bit integer subset Basic group: RISC-like, no addressing mode One eight-core desktop workstation Group #Patterns 607 Max. Size Synthesis Time Basic 39 575 4 3:25 Load/Store 35 4:04:50:54

Application: Instruction Selection 14 2018-02-28 Sebastian Buchwald, Andreas Fried, Sebastian Hack - Synthesizing Instruction Selection IPD Turn patterns into instruction selection rules Integrated in Firm research compiler Synthesized matcher goes fjrst Handwritten matcher used as fallback Synthesized matcher covers 75.7 % of SPEC CINT2000 Greedy DAG matcher ( ≈ LLVM)