GlobalISel LLVMs Latest Instruction Selection Framework Diana Picu - - PowerPoint PPT Presentation

▶
globalisel
SMART_READER_LITE
LIVE PREVIEW

GlobalISel LLVMs Latest Instruction Selection Framework Diana Picu - - PowerPoint PPT Presentation

Jul 26, 2023 324 likes •682 views

GlobalISel LLVMs Latest Instruction Selection Framework Diana Picu Instruction Selection Target-independent IR ISel Machine-dependent IR 2 Instruction Selection define i32 @add(i32 %a, i32 %b) { entry: LLVM IR %add = add nsw i32 %b,

slide-1
SLIDE 1

GlobalISel

Diana Picuş

LLVM’s Latest Instruction Selection Framework

slide-2
SLIDE 2

Instruction Selection

Target-independent IR Machine-dependent IR

ISel

2

slide-3
SLIDE 3

Instruction Selection

LLVM IR Machine-dependent IR

ISel

define i32 @add(i32 %a, i32 %b) { entry: %add = add nsw i32 %b, %a ret i32 %add }

3

slide-4
SLIDE 4

Instruction Selection

LLVM IR MachineInstr (MIR)

ISel

define i32 @add(i32 %a, i32 %b) { entry: %add = add nsw i32 %b, %a ret i32 %add } name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

4

slide-5
SLIDE 5

Instruction Selection

LLVM IR MachineInstr

ISel

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

  • Static Single Assignment

5

slide-6
SLIDE 6

Instruction Selection

LLVM IR MachineInstr

ISel

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

  • Static Single Assignment
  • Virtual registers

6

slide-7
SLIDE 7

Instruction Selection

LLVM IR MachineInstr

ISel

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

  • Static Single Assignment
  • Virtual registers
  • Pseudoinstructions

7

slide-8
SLIDE 8

Currently in LLVM

LLVM IR MachineInstr

DAGISel

8

slide-9
SLIDE 9

Currently in LLVM

LLVM IR MachineInstr

DAGISel

Build SelectionDAG DAG combine Legalize types More DAG combine Legalize vectors Legalize types More DAG combine Legalize (operations) More DAG combine Select instructions Schedule instructions Emit MachineInstr

9

slide-10
SLIDE 10

Currently in LLVM

LLVM IR MachineInstr

DAGISel

10

slide-11
SLIDE 11

Currently in LLVM

LLVM IR MachineInstr

DAGISel FastISel

11

slide-12
SLIDE 12

In the Making

LLVM IR MachineInstr

GlobalISel

12

slide-13
SLIDE 13

In the Making

LLVM IR MachineInstr

GlobalISel

MachineInstr

+ Register banks + Generic instructions

13

slide-14
SLIDE 14

In the Making

LLVM IR MachineInstr

GlobalISel

MachineInstr Machine Passes

=>

14

slide-15
SLIDE 15

The GlobalISel Pipeline

LLVM IR MachineInstr

IRTranslator Legalizer RegBankSelect InstructionSelect

15

slide-16
SLIDE 16

IRTranslator

LLVM IR Generic MachineInstr

IRTranslator

G_ADD G_LOAD G_ANYEXT G_FRAME_INDEX G_CONSTANT G_BRCOND G_INTRINSIC G_FADD ...

16

slide-17
SLIDE 17

IRTranslator

name: add registers:

  • { id: 0, class: _ }
  • { id: 1, class: _ }
  • { id: 2, class: _ }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

IRTranslator output (Generic MIR):

17

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

Final goal of instruction selection (MIR):

slide-18
SLIDE 18

IRTranslator

name: add registers:

  • { id: 0, class: _ }
  • { id: 1, class: _ }
  • { id: 2, class: _ }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

IRTranslator output (Generic MIR):

18

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

Final goal of instruction selection (MIR):

slide-19
SLIDE 19

name: add registers:

  • { id: 0, class: _ }
  • { id: 1, class: _ }
  • { id: 2, class: _ }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

IRTranslator

IRTranslator output (Generic MIR):

19

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

Final goal of instruction selection (MIR):

Scalar sN (number of bits) Pointer pN (address space) Vector M x sN (lanes x number of bits)

slide-20
SLIDE 20

IRTranslator

name: add registers:

  • { id: 0, class: _ }
  • { id: 1, class: _ }
  • { id: 2, class: _ }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

IRTranslator output (Generic MIR):

20

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

Final goal of instruction selection (MIR):

slide-21
SLIDE 21

IRTranslator

name: add registers:

  • { id: 0, class: _ }
  • { id: 1, class: _ }
  • { id: 2, class: _ }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

IRTranslator output (Generic MIR):

21

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

Final goal of instruction selection (MIR):

slide-22
SLIDE 22

Legalizer

LLVM IR Generic MachineInstr

IRTranslator Legalizer

  • Legal
  • NarrowScalar
  • WidenScalar
  • FewerElements
  • MoreElements
  • Lower
  • Libcall
  • Custom
  • Unsupported

(operation, type)

22

slide-23
SLIDE 23

Register Bank Selection

LLVM IR Generic MachineInstr

IRTranslator Legalizer RegBankSelect

23

...

X0, W0 X1, W1 X30, W30 GPR

...

Q0, D0, S0, H0, B0 FPR Q1, D1, S1, H1, B1 Q31, D31, S31, H31, B31

slide-24
SLIDE 24

Instruction Selection

LLVM IR MachineInstr

IRTranslator Legalizer RegBankSelect InstructionSelect

24

slide-25
SLIDE 25

Instruction Selection

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

After instruction selection:

name: add registers:

  • { id: 0, class: gpr }
  • { id: 1, class: gpr }
  • { id: 2, class: gpr }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

Before instruction selection:

25

slide-26
SLIDE 26

Instruction Selection

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

After instruction selection:

name: add registers:

  • { id: 0, class: gpr }
  • { id: 1, class: gpr }
  • { id: 2, class: gpr }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

Before instruction selection:

26

slide-27
SLIDE 27

name: add registers:

  • { id: 0, class: gpr }
  • { id: 1, class: gpr }
  • { id: 2, class: gpr }

body: | bb.1.entry: liveins: %w0, %w1 %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %1, %0 %w0 = COPY %2(s32) RET_ReallyLR implicit %w0

Instruction Selection

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

After instruction selection: Before instruction selection:

27

slide-28
SLIDE 28

Instruction Selection

name: add registers:

  • { id: 0, class: gpr32 }
  • { id: 1, class: gpr32 }
  • { id: 2, class: gpr32 }

body: | bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0

28

Backend Passes

slide-29
SLIDE 29

Current Status

llc -global-isel [...] clang -mllvm -global-isel [...] llc -global-isel -global-isel-abort=0 [...]

  • Prototype, disabled by default

29

slide-30
SLIDE 30

Current Status

30

  • Work in progress: Improving the framework (e.g. TableGen)

/// General Purpose Registers: W, X. def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; /// Floating Point/Vector Registers: B, H, S, D, Q. def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. def CCRRegBank : RegisterBank<"CCR", [CCR]>;

slide-31
SLIDE 31

Current Status

31

  • Work in progress: Target adoption

○ AArch64 ■ Passes > 63% of the test-suite ■ Plans to replace FastISel this year ■ Much faster than DAGISel (but worse code) ■ Hoping to get within 1.1x of FastISel ○ ARM ○ AMDGPU ○ x86

  • Work in progress: Improving the framework (e.g. TableGen)

/// General Purpose Registers: W, X. def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; /// Floating Point/Vector Registers: B, H, S, D, Q. def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. def CCRRegBank : RegisterBank<"CCR", [CCR]>;

slide-32
SLIDE 32

Summary + Q&A

32

?

  • Status (20 January 2017):

http://lists.llvm.org/pipermail/llvm-dev/2017-January/109366.html

  • Docs: http://llvm.org/docs/GlobalISel.html
  • In depth presentation from US LLVM:

https://www.youtube.com/watch?v=6tfb344A7w8

slide-33
SLIDE 33

33

slide-34
SLIDE 34

Legalizer

34

%0(p0) = COPY %x0 %1(s128) = G_LOAD %0(p0) :: (load 16 from %ir.x) %0(p0) = COPY %x0 %13(s64) = G_CONSTANT i64 0 %12(p0) = G_GEP %0, %13(s64) %11(s64) = G_LOAD %12(p0) :: (load 16 from %ir.x) %16(s64) = G_CONSTANT i64 8 %15(p0) = G_GEP %0, %16(s64) %14(s64) = G_LOAD %15(p0) :: (load 16 from %ir.x) %9(s128) = G_SEQUENCE %11(s64), 0, %14(s64), 64

Output: Input:

slide-35
SLIDE 35

Register Bank Selection

35

%0(s64) = COPY %x0 %1(p0) = COPY %x1 %2(<2 x s32>) = G_BITCAST %0(s64) %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr) %4(<2 x s32>) = G_OR %2, %3 %5(s64) = G_BITCAST %4(<2 x s32>) %x0 = COPY %5(s64) RET_ReallyLR implicit %x0 registers:

  • { id: 0, class: gpr }
  • { id: 1, class: gpr }
  • { id: 2, class: fpr }
  • { id: 3, class: fpr }
  • { id: 4, class: fpr }
  • { id: 5, class: gpr }

registers:

  • { id: 0, class: gpr }
  • { id: 1, class: gpr }
  • { id: 2, class: gpr }
  • { id: 3, class: gpr }
  • { id: 4, class: gpr }
  • { id: 5, class: gpr }

Fast: Greedy: