GlobalISel LLVMs Latest Instruction Selection Framework Diana Picu - PowerPoint PPT Presentation

GlobalISel LLVM’s Latest Instruction Selection Framework Diana Picuş

Instruction Selection Target-independent IR ISel Machine-dependent IR 2

Instruction Selection define i32 @add(i32 %a, i32 %b) { entry: LLVM IR %add = add nsw i32 %b, %a ret i32 %add } ISel Machine-dependent IR 3

Instruction Selection define i32 @add(i32 %a, i32 %b) { entry: LLVM IR %add = add nsw i32 %b, %a ret i32 %add } ISel name: add registers: - { id: 0, class: gpr32 } - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } body: | MachineInstr bb.0.entry: liveins: %w0, %w1 (MIR) %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0 4

Instruction Selection LLVM IR ● Static Single Assignment ISel name: add registers: - { id: 0, class: gpr32 } - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } body: | MachineInstr bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0 5

Instruction Selection LLVM IR ● Static Single Assignment ● Virtual registers ISel name: add registers: - { id: 0, class: gpr32 } - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } body: | MachineInstr bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0 6

Instruction Selection LLVM IR ● Static Single Assignment ● Virtual registers ● Pseudoinstructions ISel name: add registers: - { id: 0, class: gpr32 } - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } body: | MachineInstr bb.0.entry: liveins: %w0, %w1 %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0 7

Currently in LLVM LLVM IR DAGISel MachineInstr 8

Currently in LLVM LLVM IR DAGISel Build SelectionDAG DAG combine Legalize types More DAG combine Legalize vectors Legalize types More DAG combine MachineInstr Legalize (operations) More DAG combine Select instructions Schedule instructions Emit MachineInstr 9

Currently in LLVM LLVM IR DAGISel MachineInstr 10

Currently in LLVM LLVM IR DAGISel FastISel MachineInstr 11

In the Making LLVM IR GlobalISel MachineInstr 12

In the Making LLVM IR MachineInstr GlobalISel + Register banks + Generic instructions MachineInstr 13

In the Making LLVM IR MachineInstr GlobalISel => Machine Passes MachineInstr 14

The GlobalISel Pipeline LLVM IR IRTranslator Legalizer RegBankSelect InstructionSelect MachineInstr 15

IRTranslator LLVM IR IRTranslator Generic MachineInstr G_ADD G_LOAD G_ANYEXT G_FRAME_INDEX G_CONSTANT G_BRCOND G_INTRINSIC G_FADD ... 16

IRTranslator Final goal of IRTranslator output instruction selection (Generic MIR): (MIR): name: add name: add registers: registers: - { id: 0, class: _ } - { id: 0, class: gpr32 } - { id: 1, class: _ } - { id: 1, class: gpr32 } - { id: 2, class: _ } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 17

IRTranslator Final goal of IRTranslator output instruction selection (Generic MIR): (MIR): name: add name: add registers: registers: - { id: 0, class: _ } - { id: 0, class: gpr32 } - { id: 1, class: _ } - { id: 1, class: gpr32 } - { id: 2, class: _ } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 18

IRTranslator Final goal of IRTranslator output instruction selection (Generic MIR): (MIR): name: add name: add registers: registers: - { id: 0, class: _ } - { id: 0, class: gpr32 } - { id: 1, class: _ } - { id: 1, class: gpr32 } - { id: 2, class: _ } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 Scalar sN (number of bits) Pointer pN (address space) Vector M x sN (lanes x number of bits) 19

IRTranslator Final goal of IRTranslator output instruction selection (Generic MIR): (MIR): name: add name: add registers: registers: - { id: 0, class: _ } - { id: 0, class: gpr32 } - { id: 1, class: _ } - { id: 1, class: gpr32 } - { id: 2, class: _ } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 20

IRTranslator Final goal of IRTranslator output instruction selection (Generic MIR): (MIR): name: add name: add registers: registers: - { id: 0, class: _ } - { id: 0, class: gpr32 } - { id: 1, class: _ } - { id: 1, class: gpr32 } - { id: 2, class: _ } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 21

Legalizer LLVM IR (operation, type) ● Legal IRTranslator ● NarrowScalar ● WidenScalar ● FewerElements Legalizer ● MoreElements ● Lower ● Libcall ● Custom Generic MachineInstr ● Unsupported 22

Register Bank Selection LLVM IR X0, W0 X1, W1 IRTranslator ... GPR X30, W30 Legalizer Q0, D0, S0, H0, B0 RegBankSelect Q1, D1, S1, H1, B1 ... FPR Q31, D31, S31, H31, B31 Generic MachineInstr 23

Instruction Selection LLVM IR IRTranslator Legalizer RegBankSelect InstructionSelect MachineInstr 24

Instruction Selection Before instruction After instruction selection: selection: name: add name: add registers: registers: - { id: 0, class: gpr } - { id: 0, class: gpr32 } - { id: 1, class: gpr } - { id: 1, class: gpr32 } - { id: 2, class: gpr } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 25

Instruction Selection Before instruction After instruction selection: selection: name: add name: add registers: registers: - { id: 0, class: gpr } - { id: 0, class: gpr32 } - { id: 1, class: gpr } - { id: 1, class: gpr32 } - { id: 2, class: gpr } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 26

Instruction Selection Before instruction After instruction selection: selection: name: add name: add registers: registers: - { id: 0, class: gpr } - { id: 0, class: gpr32 } - { id: 1, class: gpr } - { id: 1, class: gpr32 } - { id: 2, class: gpr } - { id: 2, class: gpr32 } body: | body: | bb.1.entry: bb.0.entry: liveins: %w0, %w1 liveins: %w0, %w1 %0(s32) = COPY %w0 %0 = COPY %w0 %1(s32) = COPY %w1 %1 = COPY %w1 %2(s32) = G_ADD %1, %0 %2 = ADDWrr %1, %0 %w0 = COPY %2(s32) %w0 = COPY %2 RET_ReallyLR implicit %w0 RET_ReallyLR implicit %w0 27

Instruction Selection name: add registers: - { id: 0, class: gpr32 } - { id: 1, class: gpr32 } - { id: 2, class: gpr32 } Backend body: | bb.0.entry: liveins: %w0, %w1 Passes %0 = COPY %w0 %1 = COPY %w1 %2 = ADDWrr %1, %0 %w0 = COPY %2 RET_ReallyLR implicit %w0 28

Current Status ● Prototype, disabled by default llc -global-isel [...] clang -mllvm -global-isel [...] llc -global-isel -global-isel-abort=0 [...] 29

Current Status ● Work in progress: Improving the framework (e.g. TableGen) /// General Purpose Registers: W, X. def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; /// Floating Point/Vector Registers: B, H, S, D, Q. def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. def CCRRegBank : RegisterBank<"CCR", [CCR]>; 30