Head First into GlobalISel Or: How to delete SelectionDAG in 100* - - PowerPoint PPT Presentation

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Head First into GlobalISel Or: How to delete SelectionDAG in 100* - - PowerPoint PPT Presentation

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Head First into GlobalISel Or: How to delete SelectionDAG in 100* easy commits 1 LLVM Dev Meeting 2017 Justin Bogner, Aditya Nandakumar, Daniel Sanders Apple Porting to GlobalISel What is the structure of a GlobalISel backend? How

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SLIDE 1

Head First into GlobalISel

Or: How to delete SelectionDAG in 100* easy commits

LLVM Dev Meeting 2017 • Justin Bogner, Aditya Nandakumar, Daniel Sanders • Apple 1

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SLIDE 2

Porting to GlobalISel

  • What is the structure of a GlobalISel backend?
  • How can we test an implementation in progress?
  • Where can we split up and parallelize work?
  • What do we need to do next?

GlobalISel Tutorial • LLVM Dev Meeting 2017 2

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SLIDE 3

A Simple Backend

GlobalISel Tutorial • LLVM Dev Meeting 2017 3

Lines of Code

AArch64 50000

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SLIDE 4

A Simple Backend

GlobalISel Tutorial • LLVM Dev Meeting 2017 4

Lines of Code

AArch64 ARM 50000

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SLIDE 5

A Simple Backend

GlobalISel Tutorial • LLVM Dev Meeting 2017 5

Lines of Code

AArch64 ARM X86 50000

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SLIDE 6

A Simple Backend

GlobalISel Tutorial • LLVM Dev Meeting 2017 6

Lines of Code

AArch64 ARM X86 AMDGPU 50000

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SLIDE 7

A Simple Backend

GlobalISel Tutorial • LLVM Dev Meeting 2017 7

Lines of Code

AArch64 ARM X86 AMDGPU BPF 50000 3000

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SLIDE 8

Lines of Code

AArch64 ARM X86 AMDGPU BPF 50000 3000

A Simple Backend

  • Working through the BPF backend as a

reference

  • 1 Register class, 1 Legal type, 1 Calling

convention

  • Will refer to AArch64 as necessary for

illustrating complexity

GlobalISel Tutorial • LLVM Dev Meeting 2017 8

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SLIDE 9

Anatomy of GlobalISel

GlobalISel Tutorial • LLVM Dev Meeting 2017 9

irtranslator legalizer regbankselect instruction-select

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SLIDE 10

Anatomy of GlobalISel

GlobalISel Tutorial • LLVM Dev Meeting 2017 10

irtranslator legalizer regbankselect instruction-select CallLowering LegalizerInfo InstructionSelector RegBankInfo

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SLIDE 11

Implementing GlobalISel

GlobalISel Tutorial • LLVM Dev Meeting 2017 11

irtranslator legalizer regbankselect instruction-select Wire up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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SLIDE 12

MIR Testing

  • GISel tests target a single pass in the pipeline
  • Test passes using -run-pass and .mir files
  • llc emits MIR when told to -stop-after machine passes
  • Use -simplify-mir to generate human-editable output

GlobalISel Tutorial • LLVM Dev Meeting 2017 12

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SLIDE 13

MIR Example

GlobalISel Tutorial • LLVM Dev Meeting 2017 13

define i32 @double(i32 %x) { %y = add i32 %x, %x ret i32 %y }

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name: double legalized: false regBankSelected: false body: | bb.0: liveins: %r1, %r2 %1:_(s64) = COPY %r1 %0:_(s32) = G_TRUNC %1(s64) %2:_(s32) = G_ADD %0, %0 %r0 = COPY %2(s32) RET implicit %r0

MIR Example

llc -global-isel -march=bpf -stop-after=irtranslator -simplify-mir

GlobalISel Tutorial • LLVM Dev Meeting 2017 14

%1:_(s64) = COPY %r1

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SLIDE 15

%1:_(s64) = COPY %r1 %1:<bank>(s64) = COPY %r1 %1:<class> = COPY %r1

Virtual Registers

VReg constraints change throughout the pipeline

GlobalISel Tutorial • LLVM Dev Meeting 2017 15

%1:_(s64) = COPY %r1

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MIR Testing

Don't match register numbers directly

GlobalISel Tutorial • LLVM Dev Meeting 2017 16

; CHECK: [[CP:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: [[TR:%[0-9]+]]:_(s32) = G_TRUNC [[CP]](s64) ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TR]], [[TR]] %1:_(s64) = COPY %r1 %0:_(s32) = G_TRUNC %1(s64) %2:_(s32) = G_ADD %0, %0

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SLIDE 17

Wire up GlobalISel

GlobalISel Tutorial • LLVM Dev Meeting 2017 17

irtranslator legalizer regbankselect instruction-select Wire up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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Subtarget Setup

Override GlobalISel API getters by backing with unique_ptrs

GlobalISel Tutorial • LLVM Dev Meeting 2017 18

BPFSubtarget : BPFGenSubtargetInfo getCallLowering(...) getRegBankInfo(...) getLegalizerInfo(...) getInstructionSelector(...)

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SLIDE 19

Initialize GlobalISel

GlobalISel Tutorial • LLVM Dev Meeting 2017 19

extern "C" void LLVMInitializeBPFTarget() { // ... auto PR = PassRegistry::getPassRegistry(); initializeGlobalISel(*PR); }

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Initialize GlobalISel Passes

Implement the hooks to provide the required passes

GlobalISel Tutorial • LLVM Dev Meeting 2017 20

BPFPassConfig : TargetPassConfig addIRTranslator(...) addLegalizeMachineIR(...) addRegBankSelect(...) addGlobalInstructionSelect(...)

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addIRTranslator(...) addLegalizeMachineIR(...) addRegBankSelect(...) addGlobalInstructionSelect(...)

Initialize GlobalISel Passes

Optionally add extra passes in between

GlobalISel Tutorial • LLVM Dev Meeting 2017 21

BPFPassConfig : TargetPassConfig addPreLegalizeMachineIR(...) addPreRegBankSelect(...) addPreGlobalInstructionSelect(...)

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Build System Bookkeeping

  • Update CMakeLists.txt with each .cpp file we add
  • Add the GlobalISel dependency to LLVMBuild.txt
  • When we add .td files, also add tablegen targets

GlobalISel Tutorial • LLVM Dev Meeting 2017 22

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Does Anything Work Yet?

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 23

define void @f() { ret void }

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SLIDE 24

Does Anything Work Yet?

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 24 0 llc 0x00000001076873f8 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 40 1 llc 0x0000000107687ab6 SignalHandler(int) + 470 2 libsystem_platform.dylib 0x00007fff730f3f5a _sigtramp + 26 3 libsystem_platform.dylib 0x0000000111a8b250 _sigtramp + 2660856592 4 llc 0x0000000106e1a2a4 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 180 5 llc 0x00000001070ecc5d llvm::FPPassManager::runOnFunction(llvm::Function&) + 509 6 llc 0x00000001070eced3 llvm::FPPassManager::runOnModule(llvm::Module&) + 67 7 llc 0x00000001070ed410 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 944 8 llc 0x0000000105e69813 compileModule(char**, llvm::LLVMContext&) + 10499 9 llc 0x0000000105e66c5b main + 1419 10 libdyld.dylib 0x00007fff72e73145 start + 1 Stack dump:

  • 0. Program arguments: llc -o - -global-isel -march=bpf -stop-after=irtranslator test.ll
  • 1. Running pass 'Function Pass Manager' on module '/Users/bogner/tmp/t.ll'.
  • 2. Running pass 'IRTranslator' on function '@f'

segmentation fault

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The IR Translator

GlobalISel Tutorial • LLVM Dev Meeting 2017 25

irtranslator legalizer regbankselect instruction-select Wiring up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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Call Lowering

GlobalISel Tutorial • LLVM Dev Meeting 2017 26

IRTranslator

Uses

CallLowering

BPFCallLowering : CallLowering lowerReturn(...) lowerFormalArguments(...) lowerCall(...)

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SLIDE 27

Sketch Call Lowering

GlobalISel Tutorial • LLVM Dev Meeting 2017 27

bool BPFCallLowering::lowerReturn( MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) const { if (VReg) return false; MIRBuilder.buildInstr(BPF::RET); return true; }

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SLIDE 28

Does Anything Work Yet?

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 28

define void @f() { ret void }

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SLIDE 29

Does Anything Work Yet?

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 29

name: test_void body: | bb.0: RET

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SLIDE 30

Does Anything Work Yet?

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 30

; CHECK: name: f ; CHECK: RET define void @f() { ret void }

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SLIDE 31

Value Handlers

  • Arg handling is mostly uniform
  • Decide where the arg/return goes
  • Exact details vary
  • ValueHandler abstracts differences

GlobalISel Tutorial • LLVM Dev Meeting 2017 31

IRTranslator CallLowering ValueHandler

handleAssignments lower

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Value Handlers

GlobalISel Tutorial • LLVM Dev Meeting 2017 32

BPFHandler : ValueHandler getStackAddress(…) assignValueToAddress(…) assignValueToReg(…)

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BPF Calling Convention

We'll ignore stack handling

GlobalISel Tutorial • LLVM Dev Meeting 2017 33

// Promote ints to i64. CCIfType<[ i8, i16, i32 ], CCPromoteToType<i64>>, // Pass args in registers. CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,

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Argument Handling

GlobalISel Tutorial • LLVM Dev Meeting 2017 34

FormalArgHandler : BPFHandler assignValueToReg(...)

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void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); break; case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break; } } MIRBuilder.getMBB().addLiveIn(PhysReg); }

35 GlobalISel Tutorial • LLVM Dev Meeting 2017

Argument Handling

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void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); break; case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break; } } MIRBuilder.getMBB().addLiveIn(PhysReg); }

36 GlobalISel Tutorial • LLVM Dev Meeting 2017

Argument Handling

%ValVReg:_(s32) = COPY PhysReg

Sizes match

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void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); break; case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break; } } MIRBuilder.getMBB().addLiveIn(PhysReg); }

37 GlobalISel Tutorial • LLVM Dev Meeting 2017

Argument Handling

%tmp:_(s64) = COPY PhysReg

Extended Assign

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void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); break; case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break; } } MIRBuilder.getMBB().addLiveIn(PhysReg); }

38 GlobalISel Tutorial • LLVM Dev Meeting 2017

Argument Handling

%tmp:_(s64) = COPY PhysReg %ValVReg:_(s32) = G_TRUNC %tmp(s64)

Extended Assign

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void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); break; case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::AExt: { auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); MIRBuilder.buildTrunc(ValVReg, Copy); break; } } MIRBuilder.getMBB().addLiveIn(PhysReg); }

39 GlobalISel Tutorial • LLVM Dev Meeting 2017

Argument Handling

%tmp:_(s64) = COPY PhysReg %ValVReg:_(s32) = G_TRUNC %tmp(s64)

Extended Assign

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SLIDE 40

bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 40

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bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 41

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bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 42

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bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 43

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bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 44

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bool BPFCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef<unsigned> VRegs) { // … SmallVector<ArgInfo, 8> InArgs; unsigned i = 0; for (auto &Arg : F.args()) { ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); InArgs.push_back(OrigArg); ++i; } FormalArgHandler Handler(MIRBuilder, MRI, CC_BPF64); return handleAssignments(MIRBuilder, InArgs, Handler); }

Lower Formal Args

GlobalISel Tutorial • LLVM Dev Meeting 2017 45

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SLIDE 46

Test Lowering

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 46

; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: RET define void @f(i64 %a) { ret void }

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SLIDE 47

Test Lowering

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 47

; CHECK: [[CP:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: [[IN:%[0-9]+]]:_(s32) = G_TRUNC [[CP]] ; CHECK: RET define void @f(i32 %a) { ret void }

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struct OutgoingHandler : public BPFHandler { OutgoingHandler(…, MachineInstrBuilder &MIB) : BPFHandler(…), MIB(MIB) {} MachineInstrBuilder &MIB; // … };

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 48

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SLIDE 49

void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 49

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SLIDE 50

void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 50

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SLIDE 51

void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 51

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SLIDE 52

void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); MIB.addUse(PhysReg, RegState::Implicit); }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 52

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bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 53

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bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 54

%0:_(s64) = COPY %r1 …G_ADD… …

InsertPt RET

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bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 55

%0:_(s64) = COPY %r1 …G_ADD… …

InsertPt RET

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bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 56

%0:_(s64) = COPY %r1 …G_ADD… … %r0 = COPY %VReg

InsertPt RET implicit %r0

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SLIDE 57

bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 57

%0:_(s64) = COPY %r1 …G_ADD… … %1:_(s64) = G_ANYEXT %VReg %r0 = COPY %1

InsertPt RET implicit %r0

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SLIDE 58

bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, unsigned VReg) { auto MIB = MIRBuilder.buildInstrNoInsert(BPF::RET); bool Success = true; if (VReg) { // … ArgInfo OrigArg{VReg, Val->getType()}; setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); OutgoingHandler Handler(MIRBuilder, MRI, RetCC_BPF64, MIB); Success = handleAssignments(MIRBuilder, {OrigArg}, Handler); } MIRBuilder.insertInstr(MIB); return Success; }

Lower Return

GlobalISel Tutorial • LLVM Dev Meeting 2017 58

%0:_(s64) = COPY %r1 …G_ADD… … %1:_(s64) = G_ANYEXT %VReg %r0 = COPY %1 BPF::RET implicit %r0

InsertPt

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Test ArgLowering

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 59

; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: %r0 = COPY [[IN]] ; CHECK: RET implicit %r0 define i64 @f(i64 %a) { ret i64 %a }

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Test ArgLowering

llc -global-isel -march=bpf -stop-after=irtranslator

GlobalISel Tutorial • LLVM Dev Meeting 2017 60

; CHECK: [[TMP:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: [[IN:%[0-9]+]]:_(s32) = G_TRUNC [[TMP]] ; CHECK: [[EXT:%[0-9]+]]:_(s64) = G_ANYEXT [[IN]] ; CHECK: %r0 = COPY [[EXT]] define i32 @f(i32 %a) { ret i32 %a }

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SLIDE 61

Register Banks

GlobalISel Tutorial • LLVM Dev Meeting 2017 61

irtranslator legalizer regbankselect instruction-select Wiring up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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SLIDE 62

Register Banks

  • Group register classes, ignoring size and type
  • Different banks imply transferring values is costly
  • A typical split is general purpose vs floating point

GlobalISel Tutorial • LLVM Dev Meeting 2017 62

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SLIDE 63

Define Register Banks

Define a bank for BPF's GPRs in BPFRegisterBanks.td

GlobalISel Tutorial • LLVM Dev Meeting 2017 63

def AnyGPRRegBank : RegisterBank<"AnyGPR", [GPR]>;

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SLIDE 64

More Register Classes

AArch64 is a good example with more register classes

GlobalISel Tutorial • LLVM Dev Meeting 2017 64

GPR32 GPR32sp GPR32common GPR32all GPR32sponly tcGPR64 GPR64 GPR64sp GPR64common GPR64all GPR64sponly CCR FPR8 FPR16 FPR32 FPR64 DD FPR128 DDD DDDD QQ QQQ QQQQ

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SLIDE 65

AArch64 Register Banks

GlobalISel Tutorial • LLVM Dev Meeting 2017 65

GPR32 GPR32sp GPR32common GPR32all GPR32sponly tcGPR64 GPR64 GPR64sp GPR64common GPR64all GPR64sponly

GPR FPR CC

CCR FPR8 FPR16 FPR32 FPR64 DD FPR128 DDD DDDD QQ QQQ QQQQ

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SLIDE 66

AArch64 Register Banks

We only need to specify the largest register class to define each bank

GlobalISel Tutorial • LLVM Dev Meeting 2017 66

/// General Purpose Registers: W, X. def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; /// Floating Point/Vector Registers: B, H, S, D, Q. def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. def CCRegBank : RegisterBank<"CC", [CCR]>;

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Generated Bank Info

GlobalISel Tutorial • LLVM Dev Meeting 2017 67

class BPFGenRegisterBankInfo : public RegisterBankInfo { protected: #define GET_TARGET_REGBANK_CLASS #include "BPFGenRegisterBank.inc" };

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Register Bank Mapping

GlobalISel Tutorial • LLVM Dev Meeting 2017 68

BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...)

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SLIDE 69

Register Bank Mapping

Given a register class, return the register bank

GlobalISel Tutorial • LLVM Dev Meeting 2017 69

BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...)

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Register Bank Mapping

GlobalISel Tutorial • LLVM Dev Meeting 2017 70

BPFRegisterBankInfo : BPFGenRegisterBankInfo getRegBankFromRegClass(...) getInstrMapping(...) getInstrAlternativeMappings(...)

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getInstrMapping

Leverage getInstrMappingImpl to handle generic instructions

GlobalISel Tutorial • LLVM Dev Meeting 2017 71

const auto &Mapping = getInstrMappingImpl(MI); if (Mapping.isValid()) return Mapping;

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SLIDE 72

getInstrMapping

Map each operand to an appropriate bank for target instructions

GlobalISel Tutorial • LLVM Dev Meeting 2017 72

SmallVector<const ValueMapping *, 8> ValMappings(NumOperands); for (unsigned Idx = 0; Idx < NumOperands; ++Idx) { if (MI.getOperand(Idx).isReg()) { LLT Ty = MRI.getType(MI.getOperand(Idx).getReg()); auto Size = Ty.getSizeInBits(); ValMappings[Idx] = &getValueMapping(0, Size, BPF::AnyGPRRegBank); } }

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SLIDE 73

Test Bank Selection

llc -march=bpf -global-isel -run-pass=regbankselect

GlobalISel Tutorial • LLVM Dev Meeting 2017 73

; CHECK-LABEL: name: defaultMapping ; CHECK: %[[CP:[0-9]+]]:anygpr(s64) = COPY %r1 ; CHECK: %[[ADD:[0-9]+]]:anygpr(s64) = G_ADD %[[CP]], %[[CP]] %0:_(s64) = COPY %r1 %1:_(s64) = G_ADD %0, %0

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SLIDE 74

getInstrAlternativeMappings

In AArch64, 32 and 64-bit "or" map equally well on FPR or GPR

GlobalISel Tutorial • LLVM Dev Meeting 2017 74

case TargetOpcode::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; }

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SLIDE 75

getInstrAlternativeMappings

In AArch64, 32 and 64-bit "or" map equally well on FPR or GPR

GlobalISel Tutorial • LLVM Dev Meeting 2017 75

case TargetOpcode::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; }

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SLIDE 76

getInstrAlternativeMappings

In AArch64, 32 and 64-bit "or" map equally well on FPR or GPR

GlobalISel Tutorial • LLVM Dev Meeting 2017 76

case TargetOpcode::G_OR: { InstructionMappings AltMappings; AltMappings.push_back(getInstructionMapping( /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size), /*NumOperands*/ 3)); AltMappings.push_back(getInstructionMapping( /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size), /*NumOperands*/ 3)); return AltMappings; }

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SLIDE 77

Legalizer

GlobalISel Tutorial • LLVM Dev Meeting 2017 77

irtranslator legalizer regbankselect instruction-select Wiring up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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SLIDE 78

Legalizer

  • Transform gMIR into legal instructions
  • Legal is defined as
  • Selectable by target
  • Operating on vregs that can be loaded/stored
  • No SelectionDAG like type legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 78

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SLIDE 79

Legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 79

Legalizer LegalizerHelper

Uses Uses

LegalizerInfo

Pass Drives Legalization Specifies Legality Helpers for Common Operations

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SLIDE 80

Legality Specifiers

GlobalISel Tutorial • LLVM Dev Meeting 2017 80

setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction)

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SLIDE 81

Legality Specifiers

GlobalISel Tutorial • LLVM Dev Meeting 2017 81

setAction({G_ADD, s64}, Legal); // Want 64 bit Dest
 setAction({G_ADD, s32}, WidenScalar);

setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction)

%2:_(s64) = G_ADD %0, %1 %3:_(s32) = … %4:_(s32) = G_ADD %3, %3

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SLIDE 82

setAction({G_ADD, s64}, Legal); // Want 64 bit Dest
 setAction({G_ADD, s32}, WidenScalar); %2:_(s64) = G_ADD %0, %1 %3:_(s32) = … %4:_(s32) = G_ADD %3, %3

Legality Specifiers

GlobalISel Tutorial • LLVM Dev Meeting 2017 82

setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction)

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SLIDE 83

setAction({G_ADD, s64}, Legal); // Want 64 bit Dest setAction({G_ADD, s32}, WidenScalar); %2:_(s64) = G_ADD %0, %1 %3:_(s32) = … %5:_(s64) = G_ANYEXT %3(s32) %6:_(s64) = G_ADD %5, %5

Legality Specifiers

GlobalISel Tutorial • LLVM Dev Meeting 2017 83

setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction)

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SLIDE 84

%2:_(s64) = G_ADD %0, %1 %3:_(s32) = … %5:_(s64) = G_ANYEXT %3(s32) %6:_(s64) = G_ADD %5, %5 setAction({G_ANYEXT, 0, s64}, Legal); setAction({G_ANYEXT, 1, s32}, Legal);

Legality Specifiers

GlobalISel Tutorial • LLVM Dev Meeting 2017 84

setAction({Opcode, [OperandIdx,] Ty}, LegalizeAction)

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SLIDE 85

Legalization in BPF

  • Set LegalizerAction in the constructor.
  • Implement legalizeCustom for custom hook if required.

GlobalISel Tutorial • LLVM Dev Meeting 2017 85

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SLIDE 86

BPFLegalizerInfo::BPFLegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); // … const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32, s64}) setAction({G_IMPLICIT_DEF, Ty}, Legal); setAction({G_PHI, s64}, Legal); for (auto Ty : {s1, s8, s16, s32}) setAction({G_PHI, Ty}, WidenScalar); // … computeTables(); }

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 86

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SLIDE 87

BPFLegalizerInfo::BPFLegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); // … const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32, s64}) setAction({G_IMPLICIT_DEF, Ty}, Legal); setAction({G_PHI, s64}, Legal); for (auto Ty : {s1, s8, s16, s32}) setAction({G_PHI, Ty}, WidenScalar); // … computeTables(); }

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 87

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SLIDE 88

BPFLegalizerInfo::BPFLegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); // … const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32, s64}) setAction({G_IMPLICIT_DEF, Ty}, Legal); setAction({G_PHI, s64}, Legal); for (auto Ty : {s1, s8, s16, s32}) setAction({G_PHI, Ty}, WidenScalar); // … computeTables(); }

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 88

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SLIDE 89

BPFLegalizerInfo::BPFLegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); // … const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32, s64}) setAction({G_IMPLICIT_DEF, Ty}, Legal); setAction({G_PHI, s64}, Legal); for (auto Ty : {s1, s8, s16, s32}) setAction({G_PHI, Ty}, WidenScalar); // … computeTables(); }

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 89

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SLIDE 90

BPFLegalizerInfo::BPFLegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); // … const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32, s64}) setAction({G_IMPLICIT_DEF, Ty}, Legal); setAction({G_PHI, s64}, Legal); for (auto Ty : {s1, s8, s16, s32}) setAction({G_PHI, Ty}, WidenScalar); // … computeTables(); }

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 90

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SLIDE 91

Test Legalizer

llc -march=bpf -global-isel -run-pass=legalizer

GlobalISel Tutorial • LLVM Dev Meeting 2017 91

; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: %r0 = COPY [[IN]] ; CHECK: RET implicit %r0 %0:_(s64) = COPY %r1 %r0 = COPY %0(s64) RET implicit %r0

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SLIDE 92

Test Legalizer

LLVM ERROR: unable to legalize instruction

GlobalISel Tutorial • LLVM Dev Meeting 2017 92

%0:_(s64) = COPY %r1 %1:_(s64) = G_ADD %0, %0 %r0 = COPY %1(s64) RET implicit %r0

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SLIDE 93

setAction({G_ADD, s64}, Legal); for (const auto &Ty : {s1, s8, s16, s32}) setAction({G_ADD, Ty}, WidenScalar);

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 93

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SLIDE 94

setAction({G_ADD, s64}, Legal); for (const auto &Ty : {s1, s8, s16, s32}) setAction({G_ADD, Ty}, WidenScalar);

BPFLegalizerInfo

GlobalISel Tutorial • LLVM Dev Meeting 2017 94

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SLIDE 95

Test Legalizer

GlobalISel Tutorial • LLVM Dev Meeting 2017 95

; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD %0:_(s64) = COPY %r1 %1:_(s64) = G_ADD %0, %0 %r0 = COPY %1(s64) RET implicit %r0

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SLIDE 96

Test Legalizer

GlobalISel Tutorial • LLVM Dev Meeting 2017 96

; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD %0:_(s64) = COPY %r1 %1:_(s32) = G_TRUNC %0 %2:_(s32) = G_ADD %1, %1 ; ...

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SLIDE 97

Custom Legalization

  • Implement legalizeCustom method
  • Specify LegalizationAction as Custom
  • Legalize G_SELECT into pseudo instruction (BPF_SELECT_CC)

GlobalISel Tutorial • LLVM Dev Meeting 2017 97

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SLIDE 98

%4:_(s64) = BPF_SELECT_CC %0, %1, <pred>, %5, %6 %2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

Custom Legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 98

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SLIDE 99

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 %4:_(s64) = BPF_SELECT_CC %0, %1, <pred>, %5, %6

Custom Legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 99

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SLIDE 100

Custom Legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 100

def BPF_SELECT_CC : Pseudo<(outs type1:$dst), (ins type0:$lhs, type0:$rhs, i64imm:$cc, type1:$true, type1:$false), “BPF_SELECT_CC\t$dst, $lhs, $rhs, $cc, $true, $false", []>;

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SLIDE 101

Custom Legalization

GlobalISel Tutorial • LLVM Dev Meeting 2017 101

setAction({G_SELECT, 1, s1}, Legal); for (const auto &Ty : {s1, s8, s16, s32}) setAction({G_SELECT, Ty}, WidenScalar); setAction({G_SELECT, s64}, Custom);

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SLIDE 102

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 102

bool BPFLegalizerInfo::legalizeCustom(…) { switch (MI.getOpcode()) { default: llvm_unreachable("Illegal Opcode"); case TargetOpcode::G_SELECT: return legalizeCustomSelect(MI, MRI, MIRBuilder); } }

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SLIDE 103

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 103

bool BPFLegalizerInfo::legalizeCustomSelect( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const { // … }

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

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SLIDE 104

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 104

MachineOperand &Op0 = MI.getOperand(0); LLT DstTy = MRI.getType(Op0.getReg()); MachineOperand &CmpOp = MI.getOperand(1); MachineOperand &Res1 = MI.getOperand(2); MachineOperand &Res2 = MI.getOperand(3);

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SLIDE 105

MachineOperand &Op0 = MI.getOperand(0); LLT DstTy = MRI.getType(Op0.getReg()); MachineOperand &CmpOp = MI.getOperand(1); MachineOperand &Res1 = MI.getOperand(2); MachineOperand &Res2 = MI.getOperand(3);

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 105

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SLIDE 106

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 106

MachineInstr *DefMI = MRI.getVRegDef(CmpOp.getReg()); if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != TargetOpcode::G_ICMP) return false;

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SLIDE 107

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineInstr *DefMI = MRI.getVRegDef(CmpOp.getReg()); if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != TargetOpcode::G_ICMP) return false;

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 107

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SLIDE 108

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineInstr *DefMI = MRI.getVRegDef(CmpOp.getReg()); if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != TargetOpcode::G_ICMP) return false;

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 108

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SLIDE 109

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineInstr *DefMI = MRI.getVRegDef(CmpOp.getReg()); if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != TargetOpcode::G_ICMP) return false;

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 109

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SLIDE 110

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineInstr *DefMI = MRI.getVRegDef(CmpOp.getReg()); if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != TargetOpcode::G_ICMP) return false;

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 110

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SLIDE 111

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 111

MachineOperand &C1 = DefMI->getOperand(2); MachineOperand &C2 = DefMI->getOperand(3); MachineOperand &PredOp = DefMI->getOperand(1);

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SLIDE 112

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineOperand &C1 = DefMI->getOperand(2); MachineOperand &C2 = DefMI->getOperand(3); MachineOperand &PredOp = DefMI->getOperand(1);

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 112

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SLIDE 113

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MachineOperand &C1 = DefMI->getOperand(2); MachineOperand &C2 = DefMI->getOperand(3); MachineOperand &PredOp = DefMI->getOperand(1);

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 113

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SLIDE 114

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 114

// Get the dest reg unsigned DstReg = MI.getOperand(0).getReg(); MIRBuilder.setInstr(MI);

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SLIDE 115

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 // Get the dest reg unsigned DstReg = MI.getOperand(0).getReg(); MIRBuilder.setInstr(MI);

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 115

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SLIDE 116

%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 // Get the dest reg unsigned DstReg = MI.getOperand(0).getReg(); MIRBuilder.setInstr(MI);

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 116

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auto Cst = MIRBuilder.buildConstant( DstTy, (unsigned)PredKind); %2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 117

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 118

MIRBuilder.buildInstr(BPF::BPF_SELECT_CC, DstReg) .addReg(Cmp1.getReg()) .addReg(Cmp2.getReg()) .addReg(Cst->getOperand(0).getReg()) .addReg(Res1.getReg()) .addReg(Res2.getReg());

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MIRBuilder.buildInstr(BPF::BPF_SELECT_CC, DstReg) .addReg(Cmp1.getReg()) .addReg(Cmp2.getReg()) .addReg(Cst->getOperand(0).getReg()) .addReg(Res1.getReg()) .addReg(Res2.getReg());

legalizeCustom

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64) %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MIRBuilder.buildInstr(BPF::BPF_SELECT_CC, DstReg) .addReg(Cmp1.getReg()) .addReg(Cmp2.getReg()) .addReg(Cst->getOperand(0).getReg()) .addReg(Res1.getReg()) .addReg(Res2.getReg());

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 120

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64), %1 %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MIRBuilder.buildInstr(BPF::BPF_SELECT_CC, DstReg) .addReg(Cmp1.getReg()) .addReg(Cmp2.getReg()) .addReg(Cst->getOperand(0).getReg()) .addReg(Res1.getReg()) .addReg(Res2.getReg());

legalizeCustom

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6 %4:_(s64) = G_SELECT %3(s1), %5(s64), %6 MIRBuilder.buildInstr(BPF::BPF_SELECT_CC, DstReg) .addReg(Cmp1.getReg()) .addReg(Cmp2.getReg()) .addReg(Cst->getOperand(0).getReg()) .addReg(Res1.getReg()) .addReg(Res2.getReg());

legalizeCustom

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6 %4:_(s64) = G_SELECT %3(s1), %5(s64), %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 123

MI.eraseFromParent();

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 124

MI.eraseFromParent();

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:_(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 125

auto &RB = MF.getSubtarget() .getRegBankInfo()

  • >getRegBankFromRegClass(BPF::GPRRegClass);

MRI.setRegBank(DstReg, RB);

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:anygpr(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6

legalizeCustom

GlobalISel Tutorial • LLVM Dev Meeting 2017 126

auto &RB = MF.getSubtarget() .getRegBankInfo()

  • >getRegBankFromRegClass(BPF::GPRRegClass);

MRI.setRegBank(DstReg, RB);

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%2:_(s64) = G_ICMP <pred>, %0(s64), %1(s64) %3:_(s1) = G_TRUNC %2(s64) %7:_(s64) = G_CONSTANT pred_kind %4:anygpr(s64) = BPF_SELECT_CC, %0(s64), %1, %7(s64), %5, %6

legalizeCustom

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return true;

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; CHECK-LABEL: name: checkcmplegal ; CHECK: [[A:%[0-9]+]]:_(s64) = COPY %r1 ; CHECK: [[B:%[0-9]+]]:_(s64) = COPY %r2 ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT ; CHECK: [[R:%[0-9]+]]:anygpr(s64) = BPF_SELECT_CC [[A]](s64), [[B]], [[CST]], [[A]], [[B]] ; CHECK: %r0 = COPY [[R]] %2:_(s64) = COPY %r1 %3:_(s64) = COPY %r2 %4:_(s64) = G_ICMP intpred(sgt), %2(s64), %3 %5:_(s1) = G_TRUNC %4(s64) %6:_(s64) = G_SELECT %5(s1), %2(s64), %3 %r0 = COPY %5(s64) RET implicit %r0

Test Custom Legalization

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SLIDE 129

Good Practices

✓Incrementally add instructions and write small targeted tests ✓Always use MachineIRBuilder for building instructions ✗ Don’t erase any other instruction besides the current ✗ Do not allow legality to be conditional

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Instruction Selector

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irtranslator legalizer regbankselect instruction-select Wiring up GISel CallLowering LegalizerInfo InstructionSelector RegBankInfo TargetMachine/SubTarget

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Instruction Selection

  • Importing rules from SelectionDAG
  • Converting PatLeaf and ComplexPattern
  • Handling custom SDNodes
  • What to do when the importer fails
  • Custom Selection

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Instruction Selection

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Implement select and use the tablegen-erated selectImpl BPFInstructionSelector : InstructionSelector select(...) selectImpl(...)

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Implement select

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bool BPFInstructionSelector::select(MachineInstr &I) const { // Ignore COPY's: the register allocator will handle them. if (Opcode == TargetOpcode::COPY) return true; if (selectImpl(I)) return true; return false; }

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Imported Rule Statistics

$ rm lib/Target/BPF/BPFGenGlobalISel.inc* $ ninja -v lib/Target/BPF/BPFGenGlobalISel.inc $ llvm-tblgen -gen-global-isel ... --stats ===-------------------------------------------------------------------------=== ... Statistics Collected ... ===-------------------------------------------------------------------------=== 16 gisel-emitter - Number of patterns emitted 16 gisel-emitter - Number of patterns imported from SelectionDAG 61 gisel-emitter - Number of SelectionDAG imports skipped 77 gisel-emitter - Total number of patterns

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Initial Imports

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16 61

Skipped Imported

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Import Failures

$ rm lib/Target/BPF/BPFGenGlobalISel.inc* $ ninja -v lib/Target/BPF/BPFGenGlobalISel.inc $ llvm-tblgen -gen-global-isel ... --warn-on-skipped-patterns Included from lib/Target/BPF/BPF.td:15: lib/Target/BPF/BPFInstrInfo.td:352:1: warning: Skipped pattern: Src pattern root isn't a trivial operator ... def STW : STOREi64<0x0, "u32", truncstorei32>; ^

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9 3 3 13 13 20

No equivalent Instruction (BPFISD::BR_CC) Src pattern child has predicate Src pattern root isn't a trivial operator Src pattern results and Dst MI defs differ No equivalent Instruction (BPFISD::CALL) Others

Import Failures

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SLIDE 138

Import PatLeaf

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);}]>; def i64immSExt32 : Leaf<i64, [{return isInt<32>( def i64immSExt32 : PatLeaf<i64, [{return isInt<32>(N->getSExtValue());}]>; Pat

Src pattern child has predicate (i64immSExt32)

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Imm

Import PatLeaf

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);}]>; def i64immSExt32 : PatLeaf<i64, [{return isInt<32>(N->getSExtValue());}]>; def i64immSExt32 : Leaf<i64, [{return isInt<32>( Imm

Use int64_t instead of SDNode

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SLIDE 140

Pat

Import PatLeaf

Src pattern child has predicate (BPF_CC_EQ)

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def BPF_CC_EQ : Leaf<i64, [{return N

  • >getZExtValue() == ISD::SETEQ;}]>;

def BPF_CC_EQ : PatLeaf<i64, [{return N->getZExtValue() == ISD::SETEQ;}]>;

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Import PatLeaf

Use APInt instead of SDNode

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def BPF_CC_EQ : PatLeaf<i64, [{return N->getZExtValue() == ISD::SETEQ;}]>; IntImm def BPF_CC_EQ : Imm

  • >getZExtValue() == ISD::SETEQ;}]>;

Leaf<i64, [{return

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; CHECK: %{{[0-9]}}:gpr = LD_imm64 1234 %0:anygpr(s64) = G_CONSTANT i64 1234 %r0 = COPY %0(s64)

Test Instruction Selection

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llc -march=bpf -global-isel -run-pass=instruction-select

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Import PatLeaf

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27 50

Skipped Imported

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def BPF_BR_CC : Pseudo<(outs), (ins i64imm:$cc, type0:$lhs, type0:$rhs, brtarget:$target), "BR_CC_PSEUDO\t$cc, $lhs, $rhs, $target", []>; def : GINodeEquiv<BPF_BR_CC, BPFbrcc>;

Map Custom ISD Nodes

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Pattern operator lacks an equivalent Instruction (BPFISD::BR_CC)

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Map Custom ISD Nodes

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def BPF_SELECT_CC : Pseudo<(outs type1:$dst), (ins type0:$lhs, type0:$rhs, i64imm:$cc, type1:$true, type1:$false), "BPF_SELECT_CC\t$dst, $lhs, $rhs, $cc, $true, $false", []>; def : GINodeEquiv<BPF_SELECT_CC, BPFselectcc>;

Pattern operator lacks an equivalent Instruction (BPFISD::SELECT_CC)

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Map Custom ISD Nodes

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49 28

Skipped Imported

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5 1 1 3 6 12

Src pattern root isn't a trivial operator Src pattern results and dst MI defs are different No equivalent Instruction (BPFISD::CALL) Unable to deduce gMIR opcode to handle Src ComplexPattern (ADDRri) not mapped Others

Import Failures

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SLIDE 148

Import ComplexPattern

def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>; def gi_ADDRri : GIComplexOperandMatcher<s64, "selectAddr">, GIComplexPatternEquiv<ADDRri>;

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SLIDE 149

Patterns To Match

%Root = G_FRAME_INDEX %fixedstack.0 %0 = G_CONSTANT i64 simm16 %Root = G_GEP %1, %0

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%0 = G_FRAME_INDEX %fixedstack.0 %1 = G_CONSTANT i64 simm16 %Root = G_GEP %0, %1 %Root = Any Register

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Cases To Handle

%Root = G_FRAME_INDEX %fixedstack.0 %0 = G_CONSTANT i64 simm16 %Root = G_GEP %1, %0

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%0 = G_FRAME_INDEX %fixedstack.0 %1 = G_CONSTANT i64 simm16 %Root = G_GEP %0, %1 %Root = Any Register %Root = G_GLOBAL_VALUE ...

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G_FRAME_INDEX

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%Root G_FRAME_INDEX %fixedstack.0 getVRegDef getOperand

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G_FRAME_INDEX

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return {{ [=](auto &MIB) { MIB.add(FrameIndex->getOperand(1)); }, [=](auto &MIB) { MIB.addImm(0); } }};

%0 = INST <Ops>, , %fixedstack.0 i64 0

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SLIDE 153

isBaseWithConstantOffset(Root, MRI)

Base + Offset

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G_GEP G_CONSTANT simm16 %Root %1 %0 getVRegDef getOperand

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SLIDE 154

Base + Offset

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return {{ [=](auto &MIB) { MIB.add(Gep->getOperand(1)); }, [=](auto &MIB) { MIB.addImm(Constant->getOperand(1).getImm()); } }};

%0 = INST <Ops>, , i64 simm16 %1

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G_GLOBAL_VALUE

155

G_GLOBAL_VALUE %Root getVRegDef

return None;

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SLIDE 156

Any Pointer

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%Root

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SLIDE 157

Any Pointer

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return {{ [=](auto &MIB) { MIB.add(Root); }, [=](auto &MIB) { MIB.addImm(0); } }};

%0 = INST <Ops>, , %Root i64 0

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SLIDE 158

isBaseWithConstantOffset(...) isOperandImmEqual(...) isObviouslySafeToFold(...)

Common Predicates

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SLIDE 159

Good Practices

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✗ Don't modify MIR in the predicate ✓Capture locals by value in a renderer lambda ✓Only create instructions in a renderer lambda

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SLIDE 160

Import ComplexPattern

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50 27

Skipped Imported

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SLIDE 161

Known Issues

warning: Src pattern root isn't a trivial operator (Has a predicate (unindexedload unindexed-loadextload extloadextloadi16 LoadMemVT=i16), first-failing:extload)

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[sz]extload/extload/truncstore/atomic-load/atomic-store in development

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SLIDE 162

Known Issues

def : Pat<(i64 (and (i64 GPR:$src), 0xffffffff)), (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>; warning: Dst pattern child isn't a leaf node or an MBB

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Development for multiple instruction emission will start soon

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Custom Selection

def : Pat<(i64 (and (i64 GPR:$src), 0xffffffff)), (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;

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Rule Priority

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bool BPFInstructionSelector::select(MachineInstr &I) const { // ... // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffFFFF) here if (selectImpl(I)) return true; // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffFFFF) here // ... return false; }

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SLIDE 165

Rule Priority

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bool BPFInstructionSelector::select(MachineInstr &I) const { // ... // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffFFFF) here if (selectImpl(I)) return true; // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffffff) here? // ... return false; }

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Rule Priority

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bool BPFInstructionSelector::select(MachineInstr &I) const { // ... // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffffff) here if (selectImpl(I)) // Contains (G_AND $dst, $src1, $src2) return true; // Implement (G_AND $dst, $src1, (G_CONSTANT i64 0xffffFFFF) here // ... return false; }

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Test Custom Selection

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; CHECK: %[[T0:[0-9]+]]:gpr = COPY %r0 ; CHECK: %[[T1:[0-9]+]]:gpr = SLL_ri %[[T0]], 32 ; CHECK: %[[T2:[0-9]+]]:gpr = SRL_ri %[[T1]], 32 ; CHECK: %r0 = COPY %[[T2]] liveins: %r0 %0:anygpr(s64) = COPY %r0 %1:anygpr(s64) = G_CONSTANT i64 4294967295 %2:anygpr(s64) = G_AND %0, %1 %r0 = COPY %2(s64)

llc -march=bpf -global-isel -run-pass=instruction-select

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Custom Selection

if (Opcode == TargetOpcode::G_AND) { MachineOperand *Dst = &I.getOperand(0); MachineOperand *LHS = &I.getOperand(1); MachineOperand *RHS = &I.getOperand(2);

GlobalISel Tutorial • LLVM Dev Meeting 2017 168

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32

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Custom Selection

if (MRI.getType(Dst->getReg()) == LLT::scalar(64) && RBI.getRegBank(Dst->getReg(), MRI, TRI)->getID() == BPF::AnyGPRRegBankID) {

GlobalISel Tutorial • LLVM Dev Meeting 2017 169

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32

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SLIDE 170

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32

bool LHSIsMask = isOperandImmEqual(*LHS, 0xffffffff, MRI); if (LHSIsMask) std::swap(LHS, RHS); if (LHSIsMask || isOperandImmEqual(*RHS, 0xffffffff, MRI)) {

Custom Selection

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SLIDE 171

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32

Custom Selection

GlobalISel Tutorial • LLVM Dev Meeting 2017 171

MachineIRBuilder Builder(I); auto MIB = Builder.buildInstr(BPF::SLL_ri, &BPF::GPRRegClass) .add(*LHS) .addImm(32); constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);

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SLIDE 172

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %dst:gpr = SRL_ri %1, i64 32

Custom Selection

GlobalISel Tutorial • LLVM Dev Meeting 2017 172

MIB = Builder.buildInstr(BPF::SRL_ri) .add(*Dst) .addUse(MIB->getOperand(0).getReg()) .addImm(32); constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);

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SLIDE 173

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %dst:gpr = SRL_ri %1, i64 32

Custom Selection

GlobalISel Tutorial • LLVM Dev Meeting 2017 173

I.eraseFromParent(); return true;

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SLIDE 174

%0:anygpr = G_CONSTANT i64 0xffffffff %dst:anygpr = G_AND %src:anygpr, %0 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %1:gpr = SLL_ri %src:gpr, i64 32 %dst:gpr = SRL_ri %1, i64 32 %dst:gpr = SRL_ri %1, i64 32

Custom Selection

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Dead code is automatically cleared away

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SLIDE 175

What's Left?

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1 12 50 14

Skipped Imported In Development C++

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SLIDE 176

Questions?

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177 GlobalISel Tutorial • LLVM Dev Meeting 2017