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The TAU 2016 Contest Timing Macro Modeling Jin Hu Song Chen Xin Zhao Xi Chen IBM Corp. Synopsys IBM Corp. Synopsys [Speaker] Sponsors: 1 TAU 2016 Workshop March 10 th -11 th , 2016 Motivation of Macro Modeling Performance


  1. The TAU 2016 Contest Timing Macro Modeling Jin Hu Song Chen Xin Zhao Xi Chen IBM Corp. Synopsys IBM Corp. Synopsys [Speaker] Sponsors: 1 TAU 2016 Workshop – March 10 th -11 th , 2016

  2. Motivation of Macro Modeling Performance Full-chip timing analysis can take days to complete – billions of transistors/gates Observation: Design comprised of many of the same smaller subdesigns Solution: Hierarchical and parallel design flow – analyze once and reuse timing models 2 Source: ��������������������������������������������������������������������������

  3. Motivation of Macro Modeling Performance Full-chip timing analysis can take days to complete – billions of transistors/gates Observation: Design comprised of many of the same smaller subdesigns Solution: Hierarchical and parallel design flow – analyze once and reuse timing models Source: ������������������������������� �� ��!��"��������!���������"���������������� �� 3 Source: ���������������������������������������������������������������

  4. Motivation of Macro Modeling Performance Full-chip timing analysis can take days to complete – billions of transistors/gates Observation: Design comprised of many of the same smaller subdesigns Solution: Hierarchical and parallel design flow – analyze once and reuse timing models Macro Level Core Level Chip Level VSU Core Core Core Core Core Core Timing Timing Timing Timing Timing Timing Timing Model Model Model Model Model Model Model VSU Core Core Core Core Core Core Timing Timing Timing Timing Timing Timing Timing Model Model Model Model Model Model Model Core Timing Model 4

  5. TAU 2016 Contest: Build on the Past Develop a timing macro modeler with reference timer Golden Timer: OpenTimer – top performer of TAU 2015 Contest Delay and Output Slew Calculation Separate Rise/Fall Transitions Block / Gate-level Capabilities † Path-level Capabilities (CPPR) Statistical / Multi-corner Capabilities Incremental Capabilities Industry-standard Formats (.lib, .v, .spef) † CPPR: process of removing inherent but artificial pessimism from timing tests and paths 5

  6. Model Size/Performance vs. Accuracy Original Design �� ���� ���� ���� � � �� �� ���� ���� � ��� Timing � � ��� ��� �� ���� ���� ���� � Model ���� ���� � � �� ���� �� �� ���� �� �� ���� ���� �� �� �� �� ��� ��� ���� ���� ���� ��� �� �� �� �� ���� ���� ���� Slower Usage Faster Usage Large Model Size** Small Accuracy** High Low 6 **general trends

  7. Timing Model Creation and Usage Original Design �� ���� ���� ���� � � �� �� ���� ���� � ��� Timing � � ��� ��� �� ���� ���� ���� � Model ���� ���� � � �� ���� Timing Query Out-of-Context Timing In-Context Timing ���������������������� ������ ������ acceptable threshold ��������������������� ������ ������ Pessimistic, ������ ������ ���������������������� usage dependent Evaluation based accuracy and performance – both generation and usage TAU 2016 Contest: target sign-off models (high accuracy), 7 but strongly consider intermediate usage, e.g., optimization where less accuracy is required

  8. Accuracy Evaluation ���� �� ���� � � ���� �� !���"��#�!�� �� ���� ���������� � ��� ��� ���� � � ��� �� ���� ���� ����� � ���� ���� � � �� ���� $��� �%�&��������� ������������������ ���� �� !���"��#�!�� )�� �*����� ���� ���� ���� � � ��!�+������ �� ���� �� ���� ���� ���!������, ��� � ��� ���� � � ��� ���������-.� ���� �� ���� ���� ��� � ���� ����������!.� ��� ���� ���� ���� ����(�����#� � � �� ���� ���� ������������������������ '������ �$(�������� �������������������� ������������������������ 8

  9. TAU 2016 Contest Infrastructure Provided to Contestants Evaluation Detailed Documentation Benchmarks Block-based Post-CPPR Timing Analysis Design Early and Late Design Connectivity Libraries Parasitics at Primary Inputs and Primary Outputs Verilog ( �� ) Liberty ( ���� ) SPEF ( ����� ) Timing and CPPR tutorials, file formats, timing model wrapper file ( ������ � ) ( ������� ) basics, evaluation rules, etc. Assertions Open Source Code and Binaries 1. PATMOS 2011 : NTU-Timer 5. TAU 2015 binary : 2. TAU 2013 : IITiMer iTimerC v2.0 Golden Memory Runtime 3. TAU 2014 : UI-Timer 6. OpenTimer Result* Usage ( ������! ) 4. ISPD 2013 : .spef/.lib parsers (UI-Timer v2.0) Based on TAU 2015 Accuracy Performance Previous contest winners, utilities Benchmarks Time frame: ~4 months Contest Scope: only hold, setup, RAT tests; *using OpenTimer no latches (flush segments); single-source clock tree 9

  10. Benchmarks: Binary Development 11 based on TAU 2015 Phase 1 benchmarks (3K – 100K gates) 7 based on TAU 2015 Phase 2 benchmarks (1K – 150K gates) 7 based on TAU 2015 Evaluation benchmarks (160K – 1.6M gates) Added randomized clock tree [TAU 2014] �/'0�1 ( CLOCK , initial FF ) For each remaining FF Select random location L in current tree �/'0�1 ( L , FF ) �/'0�12���.����3 : create buffer chain from ��� to ���� FF FF FF L 2 CLOCK L 1 10

  11. Benchmarks: Evaluation 10 based on TAU 2015 Phase 1 comb. benchmarks (0.2K – 1.7K gates) 9 based on TAU 2015 Phase 1 seq. benchmarks (0.1K – 1K gates) 6 based on TAU 2015 Phase 2 and Evaluation benchmarks (8.2K – 1.9M gates) Added randomized clock tree [TAU 2014] �/'0�1 ( CLOCK , initial FF ) For each remaining FF Select random location L in current tree �/'0�1 ( L , FF ) �/'0�12���.����3 : create buffer chain from ��� to ���� FF FF FF L 2 CLOCK L 1 11

  12. Evaluation Metrics Accuracy (Compared to Golden Results) Query Slack at PIs and POs Query Slack at PIs and POs in in-context design : S IC in original design : S OoC Accuracy Score (Difference) Compute Difference d S for all PIs and POs D S : 4�.��5��������� if optimistic, d S = 2 d S 2�.��5��������� 2��.��5�������� 2��.��3�������� average AVG( D S ) Average performance standard deviation STDEV( D S ) maximum MAX( D S ) Worst performance Runtime Factor (Relative) MAX_R( D ) – R( D ) Composite Design Score RF( D ) = R( D ) MAX_R( D ) – MIN_R( D ) score( D ) = A( D ) (70 + 20 RF( D ) + 10 MF( D )) Memory Factor (Relative) MAX_M( D ) – M( D ) Overall Contestant Score is MF( D ) = M( D ) MAX_M( D ) – MIN_M( D ) average over all design scores 12

  13. TAU 2016 Contestants University Team Name Drexel University Dragon University of Illinois at Urbana-Champaign LibAbs University of Minnesota, Twin Cities -- University of Thessaly too_fast_too_accurate India Institute of Technology, Madras Darth Consilius India Institute of Technology, Madras IITMTimers National Chiao Tung University iTimerM 13

  14. Contestant Results: Accuracy Top 2 Teams: Very different generated models 25 designs: Both teams have high accuracy on 21 of them ( < 1 ps max difference) Team 1: very consistent on high accuracy Benchmark Team 1 Team 2 �!�#����#����#���� 0.31 0.51 �!�#���#�����#���� 0.43 0.83 �����#�����#���� 0.42 30.7 �������#�����#���� 0.19 90.9 �����#�����#���� 0.24 126.5 Accuracy Average (all) 1.00 0.94 14

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