George Chen Amit Dhuria Intel Cadence The TAU 2017 Contest Path - - PowerPoint PPT Presentation

George Chen Amit Dhuria Intel Cadence

Programmable Solutions Group

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The TAU 2017 Contest

Path Reporting Contest

George Chen

Intel

[Speaker]

Amit Dhuria

Cadence

Xi Chen

Synopsys

Sponsors:

Programmable Solutions Group

Why Path Reporting?

Path reporting occupies a large portion of static timing analysis

• Core timing analysis is generated only once.
• But timing report generation occurs many times, after initial timing update.
• 1000s+ commands may be issued for specific subset of paths to check for

timing closure

• Web-based dashboard systems built to parse data depend upon the path

reporting infrastructure Raise awareness of the need for efficient parallelization of path reporting

• Accurate handling of from/through/to parameters
• Explore limitations to the performance of path reporting.

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Programmable Solutions Group

Contest Overview

Leveraged past TAU Timing Contest Infrastructure

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Very limited time frame: 2 months only (12/17/2017 to 2/16/2018) Contest scope: Graph-Based Analysis only, with support of

• from/-rise_from/-fall_from
• through/-rise_through/-fall_through
• to/-rise_to/fall_to

Provided to Contestants

Benchmarks

Timing and path reporting tutorials, file formats, timing model basics, evaluation rules, etc.

• 5. TAU 2015 binary:

iTimerC v2.0

• 6. OpenTimer

(UI-Timer v2.0)

Detailed Documentation

Previous contest winners, utilities Verilog (.v) Liberty (.lib) Design Parasitics SPEF (.spef) wrapper file (.tau2018)

Evaluation

~100K individual path queries across two designs

Performance (.output)

Memory Usage Golden Result* Runtime

Accuracy Early and Late Libraries Design Connectivity

Open Source Code and Binaries

• 1. PATMOS 2011: NTU-Timer
• 2. TAU 2013: IITiMer
• 3. TAU 2014: UI-Timer
• 4. ISPD 2013: .spef/.lib parsers

(.ops)

STA Run

Programmable Solutions Group

Benchmarks

Based on TAU 2015 Benchmarks Test setup

• ~50K paths per testcase pre-generated by commercial timer
• Used special constant-delay Liberty models to reduce/eliminate delay

calculation impact.

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Design Gates Nets vga_lcd 139.5K 139.6K leon3mp_iccad 1247.7K 1248.0K

Programmable Solutions Group

Evaluation Metrics

Overview Detailed Scoring Algorithm (10 points possible)

• Accuracy = 3 *

# 𝑑𝑝𝑠𝑠𝑓𝑑𝑢 𝑞𝑏𝑢ℎ𝑡 # 𝑢𝑝𝑢𝑏𝑚 𝑞𝑏𝑢ℎ𝑡 (custom script)

• Runtime = 3 *

min(𝑏𝑚𝑚 𝑓𝑜𝑢𝑠𝑗𝑓𝑡) 𝑓𝑜𝑢𝑠𝑧′𝑡 𝑠𝑣𝑜𝑢𝑗𝑛𝑓 (measured wall clock time using “time” cmd)

• Memory = 2 *

min ( 𝑏𝑚𝑚 𝑓𝑜𝑢𝑠𝑗𝑓𝑡 ) 𝑓𝑜𝑢𝑠𝑧′𝑡 𝑛𝑓𝑛𝑝𝑠𝑧 (measured peak memory using “time” cmd)

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Metric Weight Remarks Accuracy 30% Correct sub-path reported Runtime 30% Elapsed time (not user time) Memory 20% Peak memory usage, including allocated memory Documentation 20% Clear description of algorithm and features

Programmable Solutions Group

TAU 2018 Contestants

University Team National Chiao Tung University / National Taiwan University iTimerP Texas A&M University Concha-STA National Tsing Hua University BattleCats

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Pei-Yu Lee1, Hsien-Han Cheng1,Iris Hui-Ru Jiang12

1National Chiao Tung University 2National Taiwan University

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Team Name: iTimerP Pei-Yu Lee1, Hsien-Han Cheng1,Iris Hui-Ru Jiang12

1National Chiao Tung University 2National Taiwan University

Tau2018 Contest

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Outline

 Algorithm flow  Motivation  Timing graph marking  Path searching  Experimental result

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Timing Graph Marking Backward Traversing Critical Paths Report Generation Timing Graph Marking Backward Traversing Critical Paths Report Generation Timing Graph Marking Backward Traversing Critical Paths Report Generation

Algorithm Flow

Forward Propagating Arrival Time Worst Slack Calculation Initial Timing Graph Construction Timing Graph Marking Backward Traversing Critical Paths Report Generation Path Extracting Block-Based Timing Analysis

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Timing Graph Marking

 Mark each pair from endpoint to startpoint

Startpoint Endpoint

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Motivation

 For each two levels, fanin cone size < fanout cone size

– Always mark fanin first to bound fanout region

Fanin cone size = fanout cone size

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Pairwise Marking

Start Level End Level Left Level Right Level Fanin cone Fanout cone (Bounded by fanin cone) Overlapped Region

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Path Searching

 Backward traverse nodes in overlapped region  Enhanced by two techniques

– Local slack bounds – Slack priority queue

 Local slack bounds

– Record worst-k slack for each nodes – Bound if current slack is better than slack bound(best slack of the node) – Reduce redundant traversal

 Slack priority queue

– Obtain globally worst slack node during backward traversing



Use a priority queue prioritized with path slack

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Runtime & Memory Tradeoff

 Perform multiple report_timing concurrently

– Without parallelism, slowest runtime/smallest memory usage (100 sec/300MB) – With parallelism, command cache size equals to 2^8 to 2^14 gives best runtime and memory tradeoff (200 sec/300MB)

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Scalability

 Perform 2^21 (1 Million) report_timing in 20 sec/360MB  Runtime increase linearly when command size doubles

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Thank you!

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Programmable Solutions Group

2018 Contest Results

Accuracy Correct Paths Total Score Team 1 100% 3.0 Team 2 100% 3.0

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Runtime Runtime Total Score Team 1 128 1.1 Team 2 49 3.0 Memory Memory Total Score Team 1 4854800 0.9 Team 2 2252696 2.0 Documentation Score Team 1 1.5 Team 2 2.0 Totals Score Placement Team 1 6.6 2nd Place Team 2 10.0 1st Place

Song Chen Technical Chair George Chen Contest Chair Tom Spyrou General Chair

TAU 2018

Timing Contest on Path Reporting

1s 1st Pr t Prize ize

Presented to For

iTimerP

National Chiao Tung University National Taiwan University

Pei-Yu Lee, Hsien-Han Cheng, and Iris Hui-Ru Jiang

2nd

nd Prize

rize

Presented to For

BattleCat

National Tsing Hua University

Kuan-Ming Lai and Wen-Hung Hsu

TAU 2018

Timing Contest on Path Reporting

Song Chen Technical Chair George Chen Contest Chair Tom Spyrou General Chair

Programmable Solutions Group

Requests

Ideas for future contests?

• What sort of topics may be interesting to the group?

Increasing contestant participation?

• How to increase contestants?

Increasing committee participation?

• We are looking for additional individuals to help plan the contest. Please

contact George.J.Chen@intel.com if you are interested!

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Programmable Solutions Group

Acknowledgements

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Xi Chen

Contest Committee Member

Tom Spyrou

Workshop General Chair

Song Chen

Workshop Technical Chair

TAU 2018 Contestants

This contest would not have been successful without your hard work and dedication