Scaling VLSI Design Debugging with Interpolation Brian Keng and - - PowerPoint PPT Presentation

Scaling VLSI Design Debugging with Interpolation

Brian Keng and Andreas Veneris

University of Toronto

FMCAD 2009 FMCAD 2009

Outline

Introduction

Motivation Contributions

Background Debugging with Interpolation Debugging with Interpolation Experiments Conclusion

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Motivation

Debugging is a major bottleneck

Finding root cause of error Consume up to 60% of total verification time Complexity = (design size) * (# cycles)

Debugging is a resource intensive process

Manual process with GUI-based tools

Manual process with GUI-based tools Automated debuggers

• e.g. Simulation, BDDs, SAT

Need to scale to industrial sized problems

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Contributions

Scalable SAT-based debugging algorithm

Partition trace into multiple windows and analyze

each window of time-frames separately

Over-approximate time-frames not in current

window using interpolants window using interpolants

Reduce memory usage

Multiple interpolants for better accuracy

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Outline

Introduction Background

Debugging UNSAT cores and Interpolants

Debugging with Interpolation Debugging with Interpolation Experiments Conclusion

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Debugging

Erronenous Circuit Error Trace

Initial State Inputs Expected Output x1 x2

D Q FF

y

Bug: should be NOR gate

Expected Output x1 x2 q0 x1

1

x2

1

q1 y0 y1 q2

1 1 Error! Output Mismatch 1

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Automated SAT-based Debugging

[Smith, et. al TCAD ’05]

• Steps:
• 1) Unroll
• 2) Error modeling muxes
• 3) Constrain initial state,

inputs, expected outputs

• 4) Constrain number of errors

x1 x2

D Q FF

y

• 4) Constrain number of errors

x1

1,1

x2

1,1

q1,1 y1,1

1 1 1 e1=1 will allow problem to be SAT

y0 x1

1,2

x2

1,2

q1 y1,2 q1,3 y1 d0 w2

1

w1

1

w2 w1 e1

1 1

e1

1

e2

1

e2

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

UNSAT Cores and Interpolants

UNSAT core

Subset of clauses that are unsatisfiable Proof of unsatisfiability

Interpolant P, for subsets A and B, has three properties:

AP B ∧ P is unsatisfiable P only contains common variables of A and B P only contains common variables of A and B

Algorithm to generate an interpolant from proof of

unsatisfiability in the form of a Boolean circuit [McMillan, CAV’03]

) ( ) ( ) ( ) ( ) ( ) ( ) ( d c b d c d b d c a c a b a b a ∨ ∨ ∧ ∨ ∧ ∨ ∧ ∨ ∧ ∨ ∧ ∨ ∧ ∨

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Outline

Introduction Background Debugging with Interpolation

Suffix Window Debugging UNSAT Suffix Instance Prefix Window Debugging Prefix Window Debugging Scalable Debugging Algorithm Multiple Interpolants Example

Experiments Conclusion

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Suffix Window Debugging

S2 X2 X3 S0 X0 X1

T0 T1 T2 T3

Use only a suffix of the error trace Only find errors after 2nd time-frame

Y2 Y3 Y0 Y1

Observed error

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

UNSAT Suffix Instance

S2 Y2 Y3 X2 X3

T2 T3

Observed error

Use UNSAT suffix instance to learn information Case 1: UNSAT core contains no initial state

variables

All solutions found No need to analyze rest of error trace

Y2 Y3

Observed error

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

UNSAT Suffix Instance

S2 Y2 Y3 X2 X3

T2 T3

Observed error

Interpolant Interpolant

Case 2: UNSAT core has initial state variables

Generate an interpolant from UNSAT instance Erroneous behavior captured by interpolant Interpolant is over-approximation of suffix instance

Y Y

blocking S B Y X T Y X T A

N ∧

Φ ∧ = ∧ ∧ ∧ ∧ ∧ =

2 3 3 3 2 2 2

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Prefix Window Debugging

S0 Y0 Y1 X0 X1

T0 T1

S2 Y2 Y3 X2 X3

T2 T3

Interpolant Interpolant

Y0 Y1 Y2 Y3

Observed error Prefix cannot be used directly since erroneous behavior

is not constrained

Use interpolant to properly constrain erroneous behavior May get spurious solutions due to over-approximation

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Scalable Debugging Algorithm

T3 T5 T4

Interpolant Interpolant Interpolant Interpolant

Partition error trace into smaller windows Iteratively analyze each window separately

Use current instance to generate interpolant for next iteration Limit # of simultaneous time-frames analyzed

Each interpolant is potentially a weaker approximation than

the previous one

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Generating Multiple Interpolants

Iteratively removing initial state variables

from current instance until problem is SAT

Using multiple interpolants will be a closer

approximation to suffix approximation to suffix

Trade-off runtime/memory for better quality

• f results
• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Example

D Q FF

x1 x2 y1 y2 x1 e1 e1 x1

1

1 1 SAT when e1=1 Bug: should be buffer

2 time frame error trace Error cardinality: N=1

1

x1 s0 x2 e2 y1 e2 y2 x1 x2

1

y1

1

y2

1

1 1 1 1 1

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Example: Suffix Debugging

1

y1 e1 e2 x1

1

x2

1

y1

1

y2

1

1 1 1

y1 e2 e1

1

UNSAT with N=1 Generate an interpolant from UNSAT instance

Over-approximation of suffix Retains information about unsatisfiability

e2

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Example: Prefix Debugging

e2 e1

1

x1 s0 x2 e1 e2 y1 y2

1 1 SAT when e1=1

Use interpolant to constrain prefix with erroneous

behavior

Finds all solutions as when modeling the entire error

trace

1

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Outline

Introduction Background Debugging with Interpolation Experiments

Experimental Setup Experimental Results

Conclusion

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Experimental Setup

Pentium Core 2, 2.4 Ghz workstation, 8 GB

ram

10 circuits from OpenCores.org Inserted in a typical RTL error (wrong

assignment, missing case statement, incorrect assignment, missing case statement, incorrect

• perator etc.)

MiniSat 1.14 with proof logging r = number of windows

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Experimental Results

1000 Interpolant Debugging Memory (MB) r=2 r=3 r=4 10 100 1000 Interpolant Debugging Run-time (s) r=2 r=3 r=4

r=4:

57% average reduction in memory 23% average reduction in run-time 2% increase number of solutions returned

100 100 1000 Interpolant Debugging Memory (MB) Orig Debugging Memory (MB) 1 1 10 100 1000 Interpolant Debugging Run-time (s) Orig Debugging Run-time (s)

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Number of Windows

0.5 1 1.5 2 Relative Memory ac972 divider2 mem_ctrl1 spi1 vga2 0.5 1 1.5 2 Relative Runtime ac97 divider2 mem_ctrl1 spi1 vga2 1 2 3 4 Number of Windows

Runtime does not necessarily decrease with r

increases

Peak memory decreases as r increases

1 2 3 4 Number of Windows

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Multiple Interpolants

20 40 60 80 100 120 Number of Solutions single multiple

• rig

Instances from largest increase in number of

suspects

Improved quality in certain cases

20 divider2 (r=4) mrisc1 (r=4) spi1 (r=4) vga1 (r=4) vga2 (r=4) Instance

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Outline

Introduction Background Debugging with Interpolation Experiments Conclusion

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009

Conclusion

Scalable Debugging Algorithm with Interpolation

Reduces number of simultaneously analyzed clock cycles

by partitioning problem into multiple windows

Use interpolants as an over-approximation Use multiple interpolants to get a better approximation

Experimental Results Experimental Results

57% average reduction in memory 23% average reduction in run-time 2% increase in suspects

• Scaling VLSI Design Debugging with

Interpolation FMCAD 2009