Scaling VLSI Design Debugging with Interpolation Brian Keng and - PowerPoint PPT Presentation

Scaling VLSI Design Debugging with Interpolation Brian Keng and Andreas Veneris FMCAD 2009 FMCAD 2009 University of Toronto

Outline � Introduction � Motivation � Contributions � Background � Debugging with Interpolation � Debugging with Interpolation � Experiments � Conclusion Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Motivation � Debugging is a major bottleneck � Finding root cause of error � Consume up to 60% of total verification time � Complexity = (design size) * (# cycles) � Debugging is a resource intensive process � Manual process with GUI-based tools Manual process with GUI-based tools � Automated debuggers e.g. Simulation, BDDs, SAT � � Need to scale to industrial sized problems Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Contributions � Scalable SAT-based debugging algorithm � Partition trace into multiple windows and analyze each window of time-frames separately � Over-approximate time-frames not in current window using interpolants window using interpolants � Reduce memory usage � Multiple interpolants for better accuracy Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Outline � Introduction � Background � Debugging � UNSAT cores and Interpolants � Debugging with Interpolation � Debugging with Interpolation � Experiments � Conclusion Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Debugging y � Erronenous Circuit x 1 D Q x 2 � Error Trace FF � Initial State Bug: should be NOR gate � Inputs � Expected Output � Expected Output Error! Output Mismatch 0 q 0 q 1 q 2 0 x 1 0 1 x 1 1 0 x 2 0 1 x 2 1 0 0 1 y 0 y 1 Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Automated SAT-based Debugging [Smith, et. al TCAD ’05] y Steps: � x 1 D Q x 2 1) Unroll � FF 2) Error modeling muxes � 3) Constrain initial state, � inputs, expected outputs 4) Constrain number of errors 4) Constrain number of errors � � e 1 =1 will allow problem to be SAT e 1 e 1 0 q 1,1 d 0 q 1 q 1,3 0 x 1 1,1 0 1 0 x 1 1,2 e 2 w 1 0 0 1 x 2 1,1 e 2 w 1 1 1 1 x 2 1,2 0 1 0 w 2 y 0 y 1,1 0 0 y 1,2 y 1 1 w 2 1 1 Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

UNSAT Cores and Interpolants � UNSAT core � Subset of clauses that are unsatisfiable � Proof of unsatisfiability � Interpolant P, for subsets A and B, has three properties: � A � P � B ∧ P is unsatisfiable � P only contains common variables of A and B � P only contains common variables of A and B � Algorithm to generate an interpolant from proof of unsatisfiability in the form of a Boolean circuit [McMillan, CAV’03] ( ) ( ) ( ) ( ) ∨ ∧ ∨ ∧ ∨ ∧ ∨ a b a b a c a c ( ) ( ) ( ) ∧ ∨ ∧ ∨ ∧ ∨ ∨ d b d c d b c d Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Outline � Introduction � Background � Debugging with Interpolation � Suffix Window Debugging � UNSAT Suffix Instance � Prefix Window Debugging � Prefix Window Debugging � Scalable Debugging Algorithm � Multiple Interpolants � Example � Experiments � Conclusion Scaling VLSI Design Debugging with � Interpolation FMCAD 2009

Suffix Window Debugging X 0 X 1 X 2 X 3 S 0 S 2 T 0 T 1 T 2 T 3 Y 0 Y 1 Y 2 Y 3 Observed error � Use only a suffix of the error trace � Only find errors after 2nd time-frame Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

UNSAT Suffix Instance X 2 X 3 S 2 T 2 T 3 Y 2 Y 2 Y 3 Y 3 Observed error Observed error � Use UNSAT suffix instance to learn information � Case 1: UNSAT core contains no initial state variables � All solutions found � No need to analyze rest of error trace Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

UNSAT Suffix Instance X 2 X 3 S 2 T 2 T 3 Interpolant Interpolant Observed error Y Y 2 Y 3 Y � Case 2: UNSAT core has initial state variables � Generate an interpolant from UNSAT instance � Erroneous behavior captured by interpolant � Interpolant is over-approximation of suffix instance 2 2 2 3 3 3 = ∧ ∧ ∧ ∧ ∧ A T X Y T X Y 2 = ∧ Φ N ∧ B S blocking Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Prefix Window Debugging X 0 X 1 X 2 X 3 S 0 S 2 T 0 T 1 T 2 T 3 Interpolant Interpolant Y 0 Y 0 Y 1 Y 1 Y 2 Y 2 Y 3 Y 3 Observed error � Prefix cannot be used directly since erroneous behavior is not constrained � Use interpolant to properly constrain erroneous behavior � May get spurious solutions due to over-approximation Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Scalable Debugging Algorithm T 5 T 4 Interpolant Interpolant T 3 Interpolant Interpolant � Partition error trace into smaller windows � Iteratively analyze each window separately � Use current instance to generate interpolant for next iteration � Limit # of simultaneous time-frames analyzed � Each interpolant is potentially a weaker approximation than the previous one Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Generating Multiple Interpolants � Iteratively removing initial state variables from current instance until problem is SAT � Using multiple interpolants will be a closer approximation to suffix approximation to suffix � Trade-off runtime/memory for better quality of results Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Example Bug: should be buffer x 1 y 1 x 2 D Q SAT when e 1 =1 FF y 2 e 1 e 1 x 1 x 1 1 x 1 x 1 0 0 1 1 1 1 y 1 y 1 0 1 0 1 s 0 0 0 y 2 0 y 2 1 0 1 1 x 2 0 1 x 2 1 e 2 e 2 � 2 time frame error trace � Error cardinality: N=1 Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Example: Suffix Debugging e 1 x 1 1 1 y 1 0 1 y 1 0 y 1 1 0 1 e 2 0 y 2 1 0 1 e 1 1 x 2 1 e 2 e 2 � UNSAT with N=1 � Generate an interpolant from UNSAT instance � Over-approximation of suffix � Retains information about unsatisfiability Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Example: Prefix Debugging SAT when e 1 =1 e 1 x 1 0 1 y 1 0 s 0 0 0 y 2 0 1 e 2 x 2 0 1 e 2 e 1 1 � Use interpolant to constrain prefix with erroneous behavior � Finds all solutions as when modeling the entire error trace Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Outline � Introduction � Background � Debugging with Interpolation � Experiments � Experimental Setup � Experimental Results � Conclusion Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Experimental Setup � Pentium Core 2, 2.4 Ghz workstation, 8 GB ram � 10 circuits from OpenCores.org � Inserted in a typical RTL error (wrong assignment, missing case statement, incorrect assignment, missing case statement, incorrect operator etc.) � MiniSat 1.14 with proof logging � r = number of windows Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Experimental Results r=2 r=2 Interpolant Debugging Memory (MB) Interpolant Debugging Memory (MB) Interpolant Debugging Run-time (s) Interpolant Debugging Run-time (s) r=3 r=3 r=4 r=4 1000 100 1000 10 1 100 1 10 100 1000 100 1000 Orig Debugging Run-time (s) Orig Debugging Memory (MB) � r=4: � 57% average reduction in memory � 23% average reduction in run-time � 2% increase number of solutions returned Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Number of Windows 2 2 ac97 ac972 divider2 divider2 mem_ctrl1 mem_ctrl1 spi1 spi1 1.5 1.5 vga2 vga2 Relative Runtime Relative Memory 1 1 0.5 0.5 0 0 1 2 3 4 1 2 3 4 Number of Windows Number of Windows � Runtime does not necessarily decrease with r increases � Peak memory decreases as r increases Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Multiple Interpolants 120 single multiple orig 100 Number of Solutions 80 60 40 20 20 0 divider2 mrisc1 spi1 vga1 vga2 (r=4) (r=4) (r=4) (r=4) (r=4) Instance � Instances from largest increase in number of suspects � Improved quality in certain cases Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Outline � Introduction � Background � Debugging with Interpolation � Experiments � Conclusion Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009

Conclusion � Scalable Debugging Algorithm with Interpolation � Reduces number of simultaneously analyzed clock cycles by partitioning problem into multiple windows � Use interpolants as an over-approximation � Use multiple interpolants to get a better approximation � Experimental Results � Experimental Results � 57% average reduction in memory � 23% average reduction in run-time � 2% increase in suspects Scaling VLSI Design Debugging with �� Interpolation FMCAD 2009