The Design of SNAP2 National ASIC Design Engineering Center, - - PowerPoint PPT Presentation

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Feb 16, 2023 342 likes •593 views

The Design of SNAP2 National ASIC Design Engineering Center, Institute of Automation, Chinese Academy of Sciences Presenter: Qiuxiang Fan Email: qiuxiang.fan@ia.ac.cn 1 Outline Introduction Powerful FPGA High-Speed Interface

SLIDE 1

The Design of SNAP2

National ASIC Design Engineering Center, Institute

f Automation, Chinese Academy of Sciences

Presenter: Qiuxiang Fan Email: qiuxiang.fan@ia.ac.cn

SLIDE 2

Introduction
Powerful FPGA
High-Speed Interface
Mezzanine Card
Structure
Development flow
New board
Our team

Outline

SLIDE 3

SNAP2

XCKU115-FLVF1924 FPGA
Zynq XC7Z010
4xQDRII
2xDDR3
4xQSFP connectors
2 Ethernet PHY interface with RJ-

45 connectors

2xFMC HPC connectors
4xZD+ connectors
3xSMA: clock/1pps/trigger
Micro secure digital (SD)

connector

2xQuad spi flash
Usb interface
XCKU115-FLVF1924 FPGA
Zynq XC7Z010
4xQDRII
2xDDR3
4xQSFP connectors
2 Ethernet PHY interface with RJ-

45 connectors

2xFMC HPC connectors
4xZD+ connectors
3xSMA: clock/1pps/trigger
Micro secure digital (SD)

connector

2xQuad spi flash
Usb interface

SLIDE 4

SIZE:233X160mm (6U standard) SIZE:233X160mm (6U standard)

SNAP2

Mechanical Dimension of Snap2 Mechanical Dimension of Snap2

SLIDE 5

Powerful FPGA

KU115:

Highest

transceiver bandwith

Highest DSP

count

Highest on-

chip memory available

SLIDE 6

Powerful Interface

10/40GE(QSFP)
PCIe(QSFP)
RapidIO(QSFP)
JESD204B
HMC

SLIDE 7

Connect to10/40G Ethernet switch
Connect to RapidIO switch

SLIDE 8

Board design

(1)High-speed PCB material TU-872 SLK SP
(2)Excellent PCB stack(20 layers)
(3) Adequate power supply design(VCCINT current up to 50A)

SLIDE 9

Board design

(4)Strict skew constraints for high-speed differential

pairs(Differential pairs<=2mil,Relative propagation delay<=10mil, )

(5)Optimize the via of high-speed signal(back-drill 、 anti-pad)
(6)High-speed signal integrity test(eye-pattern 、 jitter 、 bit-error-

rate)

SLIDE 10

Powerful Mezzanine Card(FMC)——ADC

(1)ADC1x3200-12 (2)ADC1x5000-10 (3)ADC8x250-8 (4)ADC8x250-14 (1)ADC1x3200-12 (2)ADC1x5000-10 (3)ADC8x250-8 (4)ADC8x250-14

ADC1x3200-12
1x TI ADC12D1600 12bit ADC
2 inputs, 1.6 Gsps
1 inputs, 3.2 Gsps
ADC1x3200-12
1x TI ADC12D1600 12bit ADC
2 inputs, 1.6 Gsps
1 inputs, 3.2 Gsps
ADC1x5000-10
1x e2V EV10AQ190 10bit ADC
4 inputs,1.25 Gsps
2 inputs, 2.5 Gsps
1 inputs, 5 Gsps
ADC1x5000-10
1x e2V EV10AQ190 10bit ADC
4 inputs,1.25 Gsps
2 inputs, 2.5 Gsps
1 inputs, 5 Gsps
ADC8x250-8
2x Hittite HMCAD1520 8bit ADC
8 inputs, 250 MSPS@8 bits
4 inputs, 500 MSPS @8 bits
2 inputs, 1000 MSPS @8 bits
ADC8x250-8
2x Hittite HMCAD1520 8bit ADC
8 inputs, 250 MSPS@8 bits
4 inputs, 500 MSPS @8 bits
2 inputs, 1000 MSPS @8 bits
ADC8x250-14
4x TI ADS62P49 14bit ADC
8 inputs, 250 MSPS@14 bits
ADC8x250-14
4x TI ADS62P49 14bit ADC
8 inputs, 250 MSPS@14 bits

SLIDE 11

Powerful Mezzanine Card(FMC)——40/100GE&DAC

1x Euvis MD657B 12bit DAC
up to 5.5 Gsps rate
2xQSFP+ connector

(2)DAC1x5500-12 (1)2x40GE module

SLIDE 12

Structure

Snap2 plugged in 1U cabinet

SLIDE 13

Structure

Snap2 plugged in 9U cabinet

SLIDE 14

Development Flow

FPGA and Zynq Configuration The configuration circuit of Snap2 system is highly flexible: 1.User can configure the FPGA and Zynq through JTAG respectively for development and debug; 2.Both FPGA and Zynq have a Quad SPI flash for configuration. After power up, FPGA and Zynq can load or boot themselves automatically from Quad SPI flash; 3.User can reconfigure FPGA through the Ethernet port connected to FPGA; 4.User can reconfigure Zynq through the Ethernet port connected to Zynq; 5.Zynq can configure FPGA through the SelectMAP interface of FPGA.

SLIDE 15

Development Flow

1)Zynq as system controller Flexible work mode:

Zynq configure FPGA through selectMAP interface of FPGA
Zynq send commands to FPGA and receive responses from FPGA

through SPI bus

The modules in FPGA integrated by AXI4 on-chip bus

SLIDE 16

2) Microblaze as system controller

Development Flow

The modules in FPGA integrated by AXI and Wishbone on-chip bus
Support JASPER tool flow

SLIDE 17

FFT FFT Correlator Correlator PFB PFB

Based on Simulink Development Environment Based on Simulink Development Environment

SLIDE 18

Control software

System bootload control System bootload control High speed Interface Information High speed Interface Information Power voltage & Current information Power voltage & Current information Board temperature information Board temperature information Original AD data display Original AD data display

SLIDE 19

Eight 8Gb DDR4 component memories
Two 144Mb QDR component memories
A 2Gb serial peripheral interface flash memory (Quad SPI) is used to configure

FPGA

Four zQSFP+(QSFP28) connectors and cages
Two VITA 57.1 FMC HPC connectors
Three ZD+ backplane connector 。
Two Ethernet PHY interface with RJ-45 connectors
Some SMA connectors. The input trigger signal, external clock and 1pps signal

are from SMA connectors

Size ： standard 6U,233mm X

160mm X 2mm

Zynq AP Soc XC7Z010 based

system controller

UltraScale+ FPGA XCVU13P-

2IFHGA2104 is used for high-speed

peration and high-speed

interconnect ： compatibility with Virtex UltraScale+ XCVU9P- 2IFLGA2104

Our new board

SLIDE 20

FPGA resource

SLIDE 21

layout

SLIDE 22

Our team(staff)

Jie Hao Jingbin Mu Yafang Song Yuting Li Leichen Zhou Lin Shu Hui Feng Dou Wang Chengcheng Li Qiuxiang Fan Zhifeng Lv Sai Ma Meiting Zhao Liangtian Zhao

SLIDE 23

2 3

Thank you!

Email: qiuxiang.fan@ia.ac.cn