Summary of previous lecture number representation: usually twos - - PowerPoint PPT Presentation

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Summary of previous lecture number representation: usually twos - - PowerPoint PPT Presentation

May 10, 2023 272 likes •597 views

Summary of previous lecture number representation: usually twos complement, but other representations possible choice depends on hardware size, performance, development time, availability of design tools etc ALU: develop

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SLIDE 1

dt10 2011 5.1

Summary of previous lecture

  • number representation: usually two’s complement,

but other representations possible

  • choice depends on hardware size, performance,

development time, availability of design tools etc

  • ALU:
  • develop efficient, regular bit-level design from
  • bvious word-level design
  • size/performance trade-offs in different architectures

e.g. ripple-carry adder versus carry-select adder

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SLIDE 2

dt10 2011 5.2

Datapath and control: 3-step derivation

(3rd Ed: p.284-314, 4th Ed: p.300-330)

  • separate datapaths for:

– register-based instructions e.g. add, sub – memory-access instructions e.g. lw, sw – branch instructions e.g. beq, j

  • combined datapath for all instructions

– add multiplexors

  • use correct part for each instruction

– control signals for multiplexors + ALU

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SLIDE 3

dt10 2011 5.3

Register-based instructions

  • select read/write registers from operands
  • select ALU operation from opcode and function

field

  • add $5, $6, $7

# reg[5] = reg[6] + reg[7]

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SLIDE 4

dt10 2011 5.4

Memory access instructions: load

  • lw $5, offset($6)

# reg[5] = M[reg[6] + offset] assume data memory to return value in same cycle

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SLIDE 5

dt10 2011 5.5

Memory access instructions: store

  • sw $5, offset($6) # M[reg[6] + offset] = reg[5]
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SLIDE 6

dt10 2011 5.6

Combine datapaths for R-type and memory instructions: R-type flow

  • 1 register file, 1 ALU
  • ALU input mux: data from register or instruction
  • register write mux: data from ALU or memory
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SLIDE 7

dt10 2011 5.7

Combine datapaths for R-type and memory instructions: memory flow

  • 1 register file, 1 ALU
  • ALU input mux: data from register or instruction
  • register write mux: data from ALU or memory
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SLIDE 8

dt10 2011 5.8

Branch instructions

  • beq $5, $6, L
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SLIDE 9

dt10 2011 5.9

Combined datapath: without instruction memory

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SLIDE 10

dt10 2011 5.10

Combined datapath: with instruction memory

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SLIDE 11

dt10 2011 5.11

Combined datapath for R-type

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SLIDE 12

dt10 2011 5.12

Combined datapath for load

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SLIDE 13

dt10 2011 5.13

Combined datapath for branch

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SLIDE 14

dt10 2011 5.14

ALU control

  • from opcode and fn code, determine ALU control

from opcode specify instruction type constant lecture on ALU

ALU control ALU control input function code ALUOp (from control unit)

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SLIDE 15

dt10 2011 5.15

ALU control: optimisation

  • K-map for rightmost bit:

F0 or F3

  • combine ALUOp:

ALUOp1 and (F0 or F3)

insert don’t cares (Xs) since 11 never arises

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SLIDE 16

dt10 2011 5.16

Identify control signals

  • ALU: ALUOp
  • control 4 mux: RegDst, ALUSrc, MemtoReg, PCSrc
  • storage: Register Write, Memory Read/Write
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SLIDE 17

dt10 2011 5.17

Control signal summary

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SLIDE 18

dt10 2011 5.18

R-type instruction (1)

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SLIDE 19

dt10 2011 5.19

R-type instruction (2)

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SLIDE 20

dt10 2011 5.20

R-type instruction (3)

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SLIDE 21

dt10 2011 5.21

R-type instruction (4)

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SLIDE 22

dt10 2011 5.22

Load instruction (1)

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SLIDE 23

dt10 2011 5.23

Load instruction (2)

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SLIDE 24

dt10 2011 5.24

Load instruction (3)

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SLIDE 25

dt10 2011 5.25

Load instruction (4) and (5)

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SLIDE 26

dt10 2011 5.26

Branch instruction (1)

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SLIDE 27

dt10 2011 5.27

Branch instruction (2)

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SLIDE 28

dt10 2011 5.28

Control unit for single-cycle datapath

  • combinational circuit: no registers
  • 6-bit opcode input

e.g. lw 100011 (35ten)

  • 9-bit output, control mux, ALU, read/write op
  • e.g. lw:

mux memory/register ALU

  • RegDst

= 0 MemRead = 1 ALUOp = 0 Branch = 0 MemWrite = 0 MemtoReg = 1 RegWrite = 1 ALUSrc = 1

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SLIDE 29

dt10 2011 5.29

Load instruction (1)

  • lw $5,offset($6)
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SLIDE 30

dt10 2011 5.30

Load instruction (2)

  • lw $5,offset($6)
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SLIDE 31

dt10 2011 5.31

Load instruction (3)

  • lw $5,offset($6)
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SLIDE 32

dt10 2011 5.32

Load instruction (4) and (5)

  • lw $5,offset($6)