Smart Port Card Version 2 (SPC-II) Architecture William D. - - PowerPoint PPT Presentation

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Smart Port Card Version 2 (SPC-II) Architecture William D. - - PowerPoint PPT Presentation

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Smart Port Card Version 2 (SPC-II) Architecture William D. Richard, Ph.D. Washington wdr@ee.wustl.edu WASHINGTON UNIVERSITY IN ST LOUIS SPC-II Design Team William D. Richard Hardware Design John D. DeHart Integration/Test

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Washington

WASHINGTON UNIVERSITY IN ST LOUIS

wdr@ee.wustl.edu

Smart Port Card Version 2 (SPC-II) Architecture

William D. Richard, Ph.D.

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-II Design Team

  • William D. Richard

Hardware Design

  • John D. DeHart

Integration/Test

  • Mike Richards

Board Layout

  • Tom Chaney

Physical Issues

  • Ed Spitznagel

Kernel Boot Disk

  • Berkley Shands

Kernel Boot Disk

  • Amy Hawkins

FPGA VHDL

  • Jon Turner

Beer?

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-I Architecture

TI

System FPGA 64 MB EDO DRAM Intel HX North Bridge

APIC

SPC Link 16 bit 16 bit PCI BUS

IPP OPP

FPX

SWITCH

166 MHz Pentium 512 KB L2 Cache

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System FPGA Intel Embedded Module CPU North- Bridge Cache DRAM PCI Bus APIC

Addr/Data Ctrl Ctrl Addr/Data/Ctrl Intr NMI INIT

PIT PIC RTC’ BIOS ROM UART1 Interface UART2 Interface UART1 UART2

Link Interface Switch Interface

SPC-I Architecture

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SPC-I Architecture

Top Bottom

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SPC-I Architecture

Line Card Connector Switch Connector

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-I Architecture

Intel CPU Module

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SPC-I Architecture

EDO DRAM SODIMM

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-I Architecture

APIC

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-I Architecture

System FPGA

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-I Architecture

Serial Ports

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SPC-II Architecture

TI

IPP OPP

SWITCH Link

256 MB SDRAM 500/700 MHz Pentium-III 256 KB L2 Cache Intel BX North Bridge

Port 1 APIC Port 0

SPC-II 16/32 bit 32 bit PCI BUS

South Bridge

ISA Bus

ISA Devices

Super-IO

BIOS

FPGA

FPX

16 bit 16 bit

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DeHart, Richard- 6/19/2002 2:36 PM

ETX Embedded Module P-III CPU North- Bridge Video DRAM PCI Bus FPGA

Video DB15

Link Interface Switch Interface

SPC-II Architecture

South- Bridge BIOS ISA Bus I/O AGP Bus FLASH DISK IDE Bus

Keyboard Mouse Serial Ports

APIC

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Advantec PIII-500 ETX Module

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Advantec PIII-500 ETX Module

Pentium III North Bridge AGP Video South Bridge SODIMM Socket Voltage Regulator

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Advantec PIII-500 ETX Module

Planar Connectors

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SPC-II Architecture

Bottom Top

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SPC-II Architecture

Top Top Heat Spreader ETX P-III Module

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SPC-II Architecture

Bottom Top Switch Connector Line Card Connector

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SPC-II Architecture

Bottom Top APIC 256 MB SDRAM

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DeHart, Richard- 6/19/2002 2:36 PM

SPC-II Architecture

Bottom Top FPGA 32-Bit PCI Slot

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SPC-II Architecture

Bottom Top 32 MB Flash IDE Disk Keyboard Mouse Video

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SPC-II Architecture

Bottom Top 150 mAH Battery Serial Ports

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IP Traffic in from Link

TI

Port 1 APIC Port 0

Link 16/32 bit 32 bit

FPGA

16 bit

FPX

Normal IP Traffic Active IP Traffic BWfpx BWlink

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IP Traffic out to Link

TI

Port 1 APIC Port 0

Link 16/32 bit 32 bit

FPGA

16 bit

FPX

Normal IP Traffic Active IP Traffic BWfpx BWlink

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Total Traffic

  • BW SPC to/from FPX

BWfpx = (1-p)X + 3pX

Normal IP Traffic

TI

Port 1 APIC Port 0

16/32 bit 32 bit

FPGA

16 bit

FPX

Active IP Traffic BWfpx BWlink

  • BW on Link

X <= BWlink BWactive= pX = Active Traffic (1-p)X = Normal IP Traffic

TI

Port 1 APIC Port 0

16/32 bit 32 bit

FPGA

16 bit

FPX

Normal IP Traffic Active IP Traffic BWfpx BWlink

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Total Traffic

  • BW on Link

X <= BWlink (1-p)X = Normal IP Traffic pX = Active IP Traffic

  • BW SPC to/from FPX

BWfpx = (1-p)X + 3pX

  • If

p = 0.1 BWlink =1 Gb/s

  • Then

BWfpx <= .9(1Gb/s) + .3(1Gb/s) BWfpx <= 1.2Gb/s

500Mb/s 400Mb/s 300Mb/s 200Mb/s 100Mb/s BWactive 1.6 .3 1.8 .4 2.0 .5 1.4 .2 1.2 .1 BWfpx p

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SPC II FPGA Architecture

Initial Design: SPC-I Mode FPX LC Switch APIC PCI Bus Port Port 1 Port 0 SPC-II FPGA OSC

16 16 16 16 16 16 16 16

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SPC II FPGA Architecture

Initial Design: Clock Domains FPX LC Switch APIC PCI Bus Port Port 1 Port 0 SPC-II FPGA OSC

16 16 16 16 16 16 16 16

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SPC II FPGA Architecture

Final Design: Cell Routing Based on VPI/VCI FPX LC Switch APIC PCI Bus Port Port 1 Port 0 SPC-II FPGA

VPI[0]=0 64<=VCI<=127

OSC

VPI[0]=1

16 32 16/32 16/32 32 16 16 16

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SPC II FPGA Architecture

Final Design: Clock Domains FPX LC Switch APIC PCI Bus Port Port 1 Port 0 SPC-II FPGA

VPI[0]=0 64<=VCI<=127

OSC

VPI[0]=1

16 32 16/32 16/32 32 16 16 16

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SPC II FPGA Architecture

Final Design: Remote CPU Reset Via Control Cell FPX LC Switch APIC PCI Bus Port Port 1 Port 0 SPC-II FPGA

VPI[0]=0 64<=VCI<=127

OSC

VPI[0]=1

16 32 16/32 16/32 32 16 16 16

Reset

VPI[0]=1 VCI = 38

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50 100 150 200 250 300 KP/s

Packet Forwarding Rates in KP/s

SPC-I/166 SPC-II/500 SPC-II/700 SPC-I/166 88 15.5 SPC-II/500 259 23.2 SPC-II/700 245 23.2 1 CELL PACKETS 32 CELL PACKETS

SPC II Relative Performance

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50 100 150 200 250 300 KP/s

Packet Forwarding Rates in KP/s

SPC-I/166 SPC-II/500 SPC-II/700 SPC-I/166 88 SPC-II/500 259 SPC-II/700 245 1 CELL (32 BYTE) PACKETS

SPC II Relative Performance

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5 10 15 20 25 KP/s

Packet Forwarding Rates in KP/s

SPC-I/166 SPC-II/500 SPC-II/700 SPC-I/166 15.5 SPC-II/500 23.2 SPC-II/700 23.2 32 CELL (1500 BYTES) PACKETS

SPC II Relative Performance

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1 2 3 4 5 Amps

IDLING CURRENT CONSUMPTION

SPC-I/166 SPC-II/500 SPC-II/700 SPC-I/166 1 0.8 SPC-II/500 3.4 0.5 SPC-II/700 4.3 0.5 5V CURRENT 3.3V CURRENT

SPC II Power Consumption

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5 10 15 20 25 Watts

IDLING POWER CONSUMPTION

SPC-I/166 SPC-II/500 SPC-II/700 SPC-I/166 7.64 SPC-II/500 18.65 SPC-II/700 23.15 POWER

SPC II Power Consumption

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  • 133 MHz AMD Elan (Jumptec)
  • 266 MHz National Geode (Jumptec)
  • 266 MHz Mobile Intel Pentium (Jumptec)
  • 300 MHz Intel Celeron (Jumptec)
  • 300 MHz National GX1 Geode (Advantech)
  • 400 MHz Intel Celeron (Advantech)
  • 400 MHz Intel Celeron (Jumptec)
  • 400 MHz Intel Pentium III (Jumptec)

Low Power ETX Module Options

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SPC II Status/Summary

  • Initial testing has been done on 5 units
  • 118 SPC-II planars have been fabricated
  • Lot build-up and testing is underway
  • FPGA switch VHDL coding is done
  • FPGA switch place and route is underway
  • FPGA switch debug yet to do
  • Delivery to kits groups scheduled for ____.
  • Each group will get ____.