Slides for Lecture 29 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation

Slides for Lecture 29

ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

18 November, 2013

ENEL 353 F13 Section 02 Slides for Lecture 29

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Previous Lecture

Completion of “divide-by-3 counter” FSM design using

• ne-hot state encoding.

Introduction to “sequence detection” problems, and solution using Moore and Mealy FSMs. Moore and Mealy state transition diagrams for an example sequence detection problem.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Today’s Lecture

Completion of next-state and output logic design for the Mealy FSM solution to example sequence detection problem. Factoring of FSMs. Reverse-engineering an FSM: Given an FSM circuit, find a word description of what the FSM does. Introduction to timing of sequential logic. Related reading in Harris & Harris: Sections 3.4.3–3.4.6, introduction to Section 3.5.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Review: State transition diagram for Mealy FSM solution to example sequence detection problem

S0 S1 S2 S3 0/0 1/0 0/1 reset 1/0 0/0 1/0 0/0 1/0

In diagrams for Mealy FSMs, it doesn’t make sense to put output values in the state circles. Arcs are labeled in / out . in indicates the input value that causes a state

• transition. out indicates

the output value for the given input and the state that the arc is coming from.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Sequence detection example: Mealy FSM, continued

Let’s choose unsigned binary encoding of the states. Let’s make a combined state transition and output table. (We’ll go straight to the version that is based on our chosen state encoding, because for this example, that’s pretty easy to do without a version of the table that lists the states symbolically.) Let’s find next-state and output equations. Let’s draw a schematic.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Sequence detection FSMs with an “unreasonable” input signal

Let’s determine what the Moore and Mealy FSMs will do if the input A is as shown . . .

CLK

1

reset

1 1 1 1

t0 t1 t2 t3 t4 A Y (Moore) Y (Mealy)

Let’s make a few remarks.

ENEL 353 F13 Section 02 Slides for Lecture 29

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A revised traffic light problem

W N S E

• B. Blvd
• A. Ave

In regular mode, the system behaves like the system that’s already been designed. In parade mode, the system advances through the regular sequence until it gets to red for A and green for B, then stays in that state. Let’s make a block diagram showing the inputs and outputs of the new, more complex traffic light controller.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Revised traffic light problem: Most obvious FSM solution

One approach to the problem is to make a new design with eight states:

◮ four states for regular mode; ◮ four more states for parade mode.

Why are four different states needed for parade mode? The eight-state FSM idea leads to the messy state transition diagram on the next slide . . .

8-state transition diagram for traffic light system with “parade mode”

S0

LA: green LB: red LA: green LB: red LA: yellow LB: red LA: yellow LB: red LA: red LB: green LA: red LB: green LA: red LB: yellow LA: red LB: yellow

S1 S3 S2

TA TA TB TB

Reset S4 S5 S7 S6

TA TA P P P P P P R R R R R P R P TA P TA P P TA R TA R R TB R TB R

Image is taken from Figure 3.34 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Factoring FSMs

The parade-mode example is set up to make two main points:

◮ Trying to solve every synchronous sequential system

design problem with a single FSM may result in unreasonably complex FSM designs.

◮ FSMs are nevertheless a great design tool. Sometimes it

make sense to design a system as a collection of simple, collaborating FSMs. Factoring is the name given to the approach described in the second of the above two points. Let’s draw a block diagram to show how the traffic light controller with parade mode can be designed using two simple FSMs that work together.

ENEL 353 F13 Section 02 Slides for Lecture 29

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State transition diagrams for factored FSM design

LA: green LB: red LA: yellow LB: red LA: red LB: green LA: red LB: yellow

S0 S1 S3 S2

TA TA M + TB MTB

Reset Lights FSM S0

M: 0

S1

M: 1 P Reset P

Mode FSM

R R

Image is taken from Figure 3.34 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.

ENEL 353 F13 Section 02 Slides for Lecture 29

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Deriving an FSM from a schematic

The next few slides closely follow the process used in Section 3.4.5 of the textbook, but use a completely different example schematic. (It’s a good idea to study the textbook example as well as the lecture example.) The first two steps in “reverse engineering” the schematic of an FSM are:

◮ Examine circuit, stating inputs, outputs, and state bits. ◮ Write next-state and output equations.

Let’s perform those two steps for the schematic on the next slide . . .

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S0 S1 S2 A S′

2

Y2 S2 Y1 Y0 S1 S′

1

S′ S0 CLK reset r

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The next three steps are:

◮ Use next-state and output

equations to create next-state and output

• tables. (The next-state

table is ready for us on this slide, to save us all some boredom.)

◮ Reduce the next-state table

to eliminate unreachable states.

◮ Assign each valid state bit

combination a name. Let’s perform the last two of the above steps.

S2 S1 S0 A S′

2 S′ 1 S′

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ENEL 353 F13 Section 02 Slides for Lecture 29

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Completion of the example FSM derivation problem

The final three steps are:

◮ Rewrite next-state and output tables with state names. ◮ Draw state transition diagram. ◮ State in words what the FSM does.

Let’s work through these steps.

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Introduction to timing of sequential logic

For a synchronous sequential circuit design, some of the major timing concerns are . . .

◮ What are sufficient conditions on the D input of a DFF to

ensure reliable operations of the DFF? (This is called the “dynamic discipline”.)

◮ Given timing specifications for DFFs and a desired clock

period TC, what do those things say about maximum delays in combinational elements in the circuit?

◮ What can go wrong if D inputs of DFFs go 0 → 1 or

1 → 0 at the wrong time? Section 3.5 of Harris & Harris is excellent on these topics. Please read it carefully, more than once!

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Upcoming topics

Timing of sequential logic. Related reading in Harris & Harris: Section 3.5 up to the end

• f 3.5.2.