Slides for Lecture 26 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation

Slides for Lecture 26

ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

8 November, 2013

ENEL 353 F13 Section 02 Slides for Lecture 26

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Previous Lecture

Enabled flip-flops. The concept of synchronous sequential circuits. Introduction to finite state machines (FSMs). Moore and Mealy structures for FSMs.

ENEL 353 F13 Section 02 Slides for Lecture 26

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Today’s Lecture

Detailed discussion of an example from the textbook: the traffic light controller FSM. Introduction to a “divide-by-3 counter” FSM design problem. Related reading in Harris & Harris: Sections 3.4.1–3.4.2

ENEL 353 F13 Section 02 Slides for Lecture 26

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Traffic light problem: system inputs TA and TB

W N E S

• B. Blvd
• A. Ave

There are traffic sensors built in to the road. Each one indicates whether a vehicle has been near the sensor within the last several seconds. TA = (eastbound traffic on A) OR (westbound traffic on A) TB = (northbound traffic on B) OR (southbound traffic on B)

ENEL 353 F13 Section 02 Slides for Lecture 26

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Traffic light problem: system outputs LA1:0 and LB1:0

The table shows how commands will be sent from the traffic light controller to each of the four sets of red-yellow-green lights. Each set of lights has two input wires. Output Encoding L1:0 green 00 yellow 01 red 10 How many output bits in total will the controller need to have? Let’s make a sketch showing all the inputs and outputs of the controller.

ENEL 353 F13 Section 02 Slides for Lecture 26

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Traffic light problem: system specification

W N E S

• B. Blvd
• A. Ave

Let’s write down a specification of the traffic light behaviour. We’ll start by specifying what should happen on a reset. (The “spec” will match what is in the textbook, pages 124–125.) Attention: We are circuit designers, not traffic engineers, so we’re going to implement the spec, not critique it!

ENEL 353 F13 Section 02 Slides for Lecture 26

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The clock for the traffic light controller

In digital design we usually think of clocks with kHz or MHz or GHz speed. But in this application the potential state updates occur once every 5 seconds. So here TC = 5 s, and fC = 1/5 s = 0.2 Hz.

ENEL 353 F13 Section 02 Slides for Lecture 26

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The state transition diagram

A key step in designing an FSM is making a state transition diagram, which shows graphically

◮ all the possible states of the system; ◮ all the possible transitions from one state to another,

with information about how the inputs affect these transitions;

◮ descriptions of how outputs are related to the state

(in Moore FSMs) or to the state and current inputs (in Mealy FSMs). Let’s make a state transition diagram for our traffic light controller (which will be a Moore FSM). Then, let’s make a few general notes about conventions for state transition diagrams for Moore FSMs.

ENEL 353 F13 Section 02 Slides for Lecture 26

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From state transition diagram to state transition table

To continue moving from specification to circuit design, a table listing the next states for all possible combinations of current state and input signals is helpful. This kind of table is called a state transition table. Use of X for don’t-care inputs can help keep the size of the table manageable. Let’s write out a state transition table for the traffic light controller. If we didn’t use X for don’t-care inputs, how many rows would the state transition table have?

ENEL 353 F13 Section 02 Slides for Lecture 26

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State encoding

In our FSM circuit, the state will be stored in DFFs in a register, so to make further progress, we will need to decide on bit patterns to represent each of the states that we have named S0, S1, S2, and S3. Let’s write out the most obvious choice of state encoding for the traffic light controller example. Important remark about notation:

◮ S0, S1, S2, S3 (with digits the same size as letters) are

names of states.

◮ S0 and S1 (with digits appearing in subscripts) identify

bits within the state register.

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A truth table for next state logic

By substituting our state encodings into the state transition table, we can get a version of the state transition table that completely specifies the next state as a combinational logic function of the current state and input variables. Let’s make that table for the traffic light controller. Let’s use the table and some K-maps to find equations for S′

1

and S′

• 0. (Harris and Harris go straight from the table to

equations, but your instructor thinks K-maps help to explain where the equations come from.)

ENEL 353 F13 Section 02 Slides for Lecture 26

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Output logic for the traffic light controller

To design output logic, we need to combine the information below into a truth table. Output L1:0 green 00 yellow 01 red 10 State, S1:0 Desired lights S0, 00 green on A, red on B S1, 01 yellow on A, red on B S2, 10 red on A, green on B S3, 11 red on A, yellow on B Let’s make the truth table, then use it to get equations for LA1, LA0, LB1, and LB0.

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From equations to a circuit . . .

¯ S1 ¯ S0 LA1 LB1 LB0 LA0 S′

1

S1 reset S1 S0 TA TB S′ S0 CLK r

The schematics in Figure 3.26 in Harris & Harris are a more compact way of representing this particular implementation of the traffic light controller.

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Review: General structure of a Moore FSM

• utput

logic next state logic state next state k k M N inputs

• utputs

CLK

It’s not hard to see how the traffic light controller fits into this framework . . .

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Moore FSM structure of traffic light controller

LA1 LB1 LB0 LA0 S′

1

S1 reset TA TB S′ S0 CLK r S1 S0

next state logic

• utput logic

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Timing diagram for the traffic light controller FSM

Figure 3.27 on page 128 of Harris & Harris is an excellent timing diagram showing behaviour of the FSM over ten example clock cycles. There’s too much detail in the diagram to make a legible slide from it. Please study the diagram and the related discussion on pages 127 and 129 carefully! It really helps in explaining typical FSM

• peration as time progresses.

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Next FSM Example: A “divide-by-3 counter”

This example is taken from Section 3.4.2 of Harris & Harris. We’ll use the example

◮ to review the steps in designing an FSM, starting from a

word description of system behaviour;

◮ to illustrate how the choice of state encoding may

influence the relative complexity of next state and output logic. Word description of the divide-by-3 counter: The only inputs are clock and reset signals. The output should be 1 during every third cycle of the input clock, and 0 during other cycles of the input clock.

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Divide-by-3 counter: Waveforms and a state transition diagram

CLK Y (a) S0 Y: 1 S1 Y: 0 S2 Y: 0 Reset (b)

Image is taken from Figure 3.28 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.

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Upcoming topics

Completion of two different divide-by-3 counter designs, and discussion of binary versus one-hot state encoding. Mealy FSM design examples. Factoring of FSMs. Reverse-engineering an FSM: Given a circuit, find a word description of what the FSM does. Related reading in Harris & Harris: Sections 3.4.2–3.4.6.