Slides for Lecture 18 ENCM 501: Principles of Computer Architecture - - PowerPoint PPT Presentation

Slides for Lecture 18

ENCM 501: Principles of Computer Architecture Winter 2014 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

18 March, 2014

ENCM 501 W14 Slides for Lecture 18

slide 2/8

Previous Lecture

◮ review of floating-numbers and operations ◮ effects of multiple-cycle EX-stage computation ◮ in-order versus out-of-order execution ◮ WAW and WAR data hazards

ENCM 501 W14 Slides for Lecture 18

slide 3/8

Today’s Lecture

◮ WHAT

Related reading in Hennessy & Patterson: Sections WHAT

ENCM 501 W14 Slides for Lecture 18

slide 4/8

Review: A slide from the previous lecture

EX M1 FP/integer multiply Integer unit FP adder FP/integer divider IF ID MEM WB M2 M3 M4 M5 M6 A1 A2 A3 A4 M7 DIV

Image is Figure C.35 from Hennessy J. L. and Patterson D. A., Computer Architecture: A Quantitative Approach, 5nd ed., c 2012, Elsevier, Inc.

ENCM 501 W14 Slides for Lecture 18

slide 5/8

More problems related to long latency

The divide unit in the Figure C.35 computer has a 24-cycle latency and is not pipelined. What kind of hazard is created by the lack of pipelining in the divide unit? What is the effect of the 4-cycle FP add latency and the 7-cycle multiply latency on the frequency and severity of RAW data hazards? (In other words, how bad are the RAW hazards, relative to how bad they could be in the simple 5-stage system that supports

• nly LW, SW, BEQ, and some integer R-type instructions?)

ENCM 501 W14 Slides for Lecture 18

slide 6/8

Review: Practical WAW hazard, and a WAR hazard

MUL.D F2, F4, F6 S.D F2, 0(R8) some hazard-free instructions L.D F2, 0(R9) ADD.D F8, F8, F2 With out-of-order (OOO) issue, L.D could complete before MUL.D, and S.D could then read the wrong value from F2—that’s an example of a WAR hazard. With OOO issue, MUL.D could write to F2 after L.D writes to F2, causing ADD.D and later instructions to use the wrong value of F2—that’s an example of a WAW hazard.

ENCM 501 W14 Slides for Lecture 18

slide 7/8

Name dependencies

The problems in the example of the previous slide stem from the decision to use F2 for two different and unrelated intermediate results. It would be safe to start L.D and ADD.D before S.D if some other register were used for the result of L.D . . . MUL.D F2, F4, F6 S.D F2, 0(R8) some hazard-free instructions L.D F10, 0(R9) ADD.D F8, F8, F10

ENCM 501 W14 Slides for Lecture 18

slide 8/8

Upcoming Topics

◮ Processing instructions with parallel pipelines.

Related reading in Hennessy & Patterson: Sections 3.1, 3.4, 3.5