Slides for Lecture 18 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation

Slides for Lecture 18

ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

21 October, 2013

ENEL 353 F13 Section 02 Slides for Lecture 18

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Previous Lecture

Completion of material on don’t-care outputs and inputs. Using K-maps to find minimal POS (not SOP) expressions. If time permitted . . . K-maps for problems with 5 inputs.

ENEL 353 F13 Section 02 Slides for Lecture 18

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Today’s Lecture

Completion of material on K-maps with 5 or 6 input bits. (Related reading in Harris & Harris: None.) Using K-maps for problems with multiple output bits. (Related reading in Harris & Harris: None.)

• Multiplexers. (Related reading in Harris & Harris: Section 2.8

introduction and Section 2.8.1.)

ENEL 353 F13 Section 02 Slides for Lecture 18

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K-maps with more than four variables

With three or four variables, adjacent cells are easy to spot, as long as you remember to look for groups that wrap around the edges of a map. With five or six variables, it’s more difficult to organize cells to make all adjacencies easy to discover. There are a few different options for setting up 5- and 6-variable maps. We’ll follow the method outlined in last year’s ENEL 353 textbook. (Marcovitz A. B., Introduction to Logic Design, 3rd ed., 2010, McGraw-Hill.)

ENEL 353 F13 Section 02 Slides for Lecture 18

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A 3-dimensional map for a 5-variable problem

We can visualize the 32-cell map this way: We look for vertical adjacencies as well as the horizontal adjacencies we’re used to finding in 4-variable maps. But marking and grouping 1-cells in a sketch like that is pretty much impossible . . .

ENEL 353 F13 Section 02 Slides for Lecture 18

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2-dimensional representation of the 3-d map

00 01 11 10 00 01 11 10 00 01 11 10 B C 00 01 11 10 D E bottom layer: A = 1 top layer: A = 0 F(A,B,C,D,E) B C D E

The five yellow cells are all adjacent to the blue cell.

ENEL 353 F13 Section 02 Slides for Lecture 18

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Example 5-variable problem

Find a minimal SOP expression for F(A,B,C,D,E) = Σ(3, 6, 11, 14, 22, 24, 28, 30)

ENEL 353 F13 Section 02 Slides for Lecture 18

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Example 5-variable problem: Solution

15 1 3 2 4 5 7 6 12 13 14 8 9 10 11

A = 0 A = 1

16 17 18 19 20 21 23 22 24 25 27 26 28 29 31 30

1 1 1 1 1 1 1 1 00 01 11 10 B C D E B C 00 01 11 10 E D 00 01 11 10 B C D E B C 00 01 11 10 E D

F(A,B,C,D,E) = ¯ A¯ CDE + AB ¯ D ¯ E + CD ¯ E

ENEL 353 F13 Section 02 Slides for Lecture 18

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6-variable K-maps

Visualize a 4 × 4 × 4 cube of 64 cells. Gray code ordering must be used in the vertical direction as well as the two horizontal directions. This year in ENEL 353 we will not do detailed examples of 6-variable K-maps, and you will not be tested on 6-variable K-maps.

ENEL 353 F13 Section 02 Slides for Lecture 18

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Multiple-output minimization problems

It’s common to have combinational logic systems that have multiple outputs depending on the same inputs. It makes sense to look for ways to share logic gates between two or more functions . . .

D A C B F G H F G H

Separate circuits for F, G, H Opportunity to share circuitry in producing F, G, H

D A C B

An example 3-output problem: Here are K-maps for function F, G, and H, with common inputs A, B, C, and D . . .

1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 01 11 10 A B C D 00 01 11 10 F(A,B,C,D) 00 01 11 10 A B C D 00 01 11 10 G(A,B,C,D) 00 01 11 10 A B C D 00 01 11 10 H(A,B,C,D)

The groupings of 1-cells above show minimal SOP expressions for each of the outputs considered independently of the other two . . . F = ¯ AD + AC ¯ D 2 AND gates, 1 OR gate G = ¯ A¯ CD + B ¯ C ¯ D 2 AND gates, 1 OR gate H = ¯ ACD + A¯ BD 2 AND gates, 1 OR gate

By splitting one of the prime implicants of F we can share products that are already in use for G and H . . .

1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 01 11 10 A B C D 00 01 11 10 F(A,B,C,D) 00 01 11 10 A B C D 00 01 11 10 G(A,B,C,D) 00 01 11 10 A B C D 00 01 11 10 H(A,B,C,D)

The number of OR gates is 3, same as before, but the number of AND gates has been reduced to 5 from 6 . . . F = ¯ A¯ CD + ¯ ACD + AC ¯ D G = ¯ A¯ CD + B ¯ C ¯ D H = ¯ ACD + A¯ BD However, the OR gate that produces F now needs 3 inputs instead of 2.

ENEL 353 F13 Section 02 Slides for Lecture 18

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Multiple-output problems: Remarks

The example shows that building minimal SOP expressions from prime implicants of individual outputs does not always minimize the overall number of products required to generate all the outputs with two-level SOP logic. Finding minimum-cost circuits for multiple output circuits has been a topic in past versions of ENEL 353, but in Fall 2013, we will not explore this topic in detail.

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Combinational building blocks

Recent lectures and reading about algebra and K-maps have been oriented towards gate-level circuit designs to implement given logic functions. However, circuit designers can often be more productive by thinking in terms of combinational building blocks, combinational elements that are more complex than simple AND, OR, NAND, NOR and XOR gates. We’ve already studied one such building block: the

• ne-bit full adder.

We’re now going to look at two more important kinds of bulding block: multiplexers and decoders.

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Multiplexers

Multiplexer is rather a long word, so mux is often used as an abbreviation. Another quite descriptive name for multiplexer is selector. A multiplexer circuit has

◮ two or more data inputs; ◮ one or more bits of select input; ◮ an output.

The job of a multiplexer is to copy one of the data inputs to the output. The data input selected for copying is chosen by the select input.

ENEL 353 F13 Section 02 Slides for Lecture 18

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The 2:1 multiplexer (“two-to-one mux”)

A circuit symbol and truth table: D0 D1

1

Y S D1 D0 S Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Let’s write out a few sentences to describe exactly what this circuit does.

ENEL 353 F13 Section 02 Slides for Lecture 18

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2:1 mux — built from NOT, AND and OR gates

The truth table from the previous slide results in this K-map and minimal SOP expression . . .

1 1 1 1

S D1 D0

00 01 11 10 1

Y = D0¯ S + D1S A circuit for this made from NOT, AND, and OR gates . . .

Y S D0 D1

ENEL 353 F13 Section 02 Slides for Lecture 18

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Variations on the tristate buffer

inverting, active low enable inverting, active high enable Y Y A A E E non-inverting, active high enable non-inverting, active low enable Y Y A A E E (a) (c) (b) (d) Version (a) is the one we have already looked at. But each of (b), (c), and (d) is sometimes useful as well. Let’s make tables to describe all four circuits.

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2:1 mux implemented with tristate buffers

The two schematics describe exactly the same design. The one

• n the right is from the textbook, and uses a compact notation for

showing a common control input wire for the tristate buffers. T0 T1 Y D1 D0 S

Y D0 S T0 T1 D1

Two gate outputs are wired together! Is that a problem in this design?

Image on right is from Figure 2.56 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.

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The 4:1 multiplexer (“four-to-one mux”)

00

D0 D1

01 10

D2 D3

11

Y S0 S1 How many rows would a truth table for this circuit have? Let’s describe the circuit in a table that is more compact than a truth table.

Let’s make some notes on these three designs for 4:1 mux circuits.

(a) Y D0 D1 D2 D3 (b) (c) S0 Y 1 1 1 S1 D0 D1 D2 D3 Y S1S0 S1S0 S1S0 S1S0 D0 D2 D3 D1 S1 S0

Image is Figure 2.58 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.

ENEL 353 F13 Section 02 Slides for Lecture 18

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Upcoming topics

Using multiplexers to implement combinational logic functions. Decoders. Related reading in Harris & Harris: Sections 2.8.1 and 2.8.2.